Kiyoo Itoh

	2012
20		Akira Kotabe, Kiyoo Itoh, Riichiro Takemura: 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs. IEICE Transactions 95-C(4): 555-563 (2012)
19		Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh: Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. IEICE Transactions 95-C(4): 594-599 (2012)
18		Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh: A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. IEICE Transactions 95-C(4): 600-608 (2012)
	2011
17		Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi: Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC 2011: 1-7
16		Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul: Beyond the horizon: The next 10x reduction in power - Challenges and solutions. ISSCC 2011: 31
15		Kiyoo Itoh: Embedded Memories: Progress and a Look into the Future. IEEE Design & Test of Computers 28(1): 10-13 (2011)
	2010
14		Kiyoo Itoh: Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs. PATMOS 2010: 255
13		Kiyoo Itoh, Masanao Yamaoka, Takashi Oshima: Adaptive Circuits for the 0.5-V Nanoscale CMOS Era. IEICE Transactions 93-C(3): 216-233 (2010)
	2009
12		Kiyoo Itoh: Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. ISLPED 2009: 273-274
11		Kiyoo Itoh: Adaptive circuits for the 0.5-V nanoscale CMOS era. ISSCC 2009: 14-20
10		Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh: Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. ISSCC 2009: 142-143
	2007
9		Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara: Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ACM Great Lakes Symposium on VLSI 2007: 529-533
8		Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara: Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. IEICE Transactions 90-C(4): 758-764 (2007)
	2006
7		Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara: Ultra-low voltage nano-scale embedded RAMs. ISCAS 2006
6		Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi: A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers. ISLPED 2006: 123-126
	2004
5		Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara: Low-Voltage Embedded RAMs - Current Status and Future Trends. PATMOS 2004: 3-15
	2003
4		Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh: Review and future prospects of low-voltage RAM circuits. IBM Journal of Research and Development 47(5-6): 525-552 (2003)
	2002
3		Kiyoo Itoh: Low-voltage memories for power-aware systems. ISLPED 2002: 1-6
2		Kiyoo Itoh: Trends in Ultralow-Voltage RAM Technology. PATMOS 2002: 300-313
	2001
1		Kiyoo Itoh, Hiroyuki Mizuno: Low-Voltage Embedded-RAM Technology: Present and Future. VLSI-SOC 2001: 277-288

Coauthor Index

1	Asad A. Abidi	[16]
2	Satoru Akiyama	[8] [10] [18]
3	Dan Dobberpuhl	[16]
4	Hermann Eul	[16]
5	Satoru Hanzawa	[8]
6	Masashi Horiguchi	[4] [7] [17]
7	Mark Horowitz	[16]
8	Kazuhiko Kajigaya	[8]
9	Takayuki Kawahara	[4] [5] [7] [8] [9]
10	Akira Kotabe	[10] [17] [18] [19] [20]
11	Philippe Magarshack	[16]
12	Hugo De Man	[16]
13	Hiroyuki Mizuno	[1]
14	Yoshinobu Nakagome	[4]
15	Kenichi Osada	[5]
16	Takashi Oshima	[13]
17	Jan M. Rabaey	[16]
18	Takayasu Sakurai	[16]
19	Tomonori Sekiguchi	[6] [8] [10] [18] [19]
20	Jack Sun	[16]
21	Riichiro Takemura	[6] [8] [10] [17] [18] [19] [20]
22	Ryuta Tsuchiya	[17]
23	Masanao Yamaoka	[9] [13]
24	Yoshimitsu Yanagawa	[19]

Colors in the list of coauthors

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