 | 2012 |
| 38 |  | Yasuaki Ito,
Koji Nakano,
Song Bo:
The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption.
IJNC 2(1): 79-96 (2012) |
| 2011 |
| 37 |  | Yuki Ago,
Atsuo Inoue,
Koji Nakano,
Yasuaki Ito:
The Parallel FDFM Processor Core Approach for Neural Networks.
ICNC 2011: 113-119 |
| 36 |  | Akihiro Uchida,
Yasuaki Ito,
Koji Nakano:
Fast and Accurate Template Matching Using Pixel Rearrangement on the GPU.
ICNC 2011: 153-159 |
| 35 |  | Yasuaki Ito,
Kohei Ogawa,
Koji Nakano:
Fast Ellipse Detection Algorithm Using Hough Transform on the GPU.
ICNC 2011: 313-319 |
| 34 |  | Kazufumi Nishida,
Yasuaki Ito,
Koji Nakano:
Accelerating the Dynamic Programming for the Matrix Chain Product on the GPU.
ICNC 2011: 320-326 |
| 33 |  | Duhu Man,
Kenji Uda,
Yasuaki Ito,
Koji Nakano:
A GPU Implementation of Computing Euclidean Distance Map with Efficient Memory Access.
ICNC 2011: 68-76 |
| 32 |  | Md. Nazrul Islam Mondal,
Koji Nakano,
Yasuaki Ito:
An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles.
ICNC 2011: 77-86 |
| 31 |  | Bo Song,
Yasuaki Ito,
Koji Nakano:
CRT-Based DSP Decryption Using Montgomery Modular Multiplication on the FPGA.
IPDPS Workshops 2011: 532-541 |
| 30 |  | Md. Nazrul Islam Mondal,
Koji Nakano,
Yasuaki Ito:
A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones.
IEICE Transactions 94-D(12): 2378-2388 (2011) |
| 29 |  | Yasuaki Ito,
Koji Nakano:
Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs.
IJNC 1(1): 49-62 (2011) |
| 28 |  | Yasuaki Ito,
Sayaka Kamei:
Preface.
IJNC 1(2): 131 (2011) |
| 27 |  | Duhu Man,
Kenji Uda,
Hironobu Ueyama,
Yasuaki Ito,
Koji Nakano:
Implementations of a Parallel Algorithm for Computing Euclidean Distance Map in Multicore Processors and GPUs.
IJNC 1(2): 260-276 (2011) |
| 26 |  | Song Bo,
Kensuke Kawakami,
Koji Nakano,
Yasuaki Ito:
An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA.
IJNC 1(2): 277-289 (2011) |
| 25 |  | Duhu Man,
Yasuaki Ito,
Koji Nakano:
An Efficient Parallel Sorting Compatible with the Standard Qsort.
Int. J. Found. Comput. Sci. 22(5): 1057-1071 (2011) |
| 2010 |
| 24 |  | Duhu Man,
Kenji Uda,
Hironobu Ueyama,
Yasuaki Ito,
Koji Nakano:
Implementations of Parallel Computation of Euclidean Distance Map in Multicore Processors and GPUs.
ICNC 2010: 120-127 |
| 23 |  | Bo Song,
Kensuke Kawakami,
Koji Nakano,
Yasuaki Ito:
An RSA Encryption Hardware Algorithm Using a Single DSP Block and a Single Block RAM on the FPGA.
ICNC 2010: 140-147 |
| 22 |  | Md. Nazrul Islam Mondal,
Koji Nakano,
Yasuaki Ito:
A Rewriting Algorithm to Generate AROM-free Fully Synchronous Circuits.
ICNC 2010: 148-155 |
| 21 |  | Kohei Ogawa,
Yasuaki Ito,
Koji Nakano:
Efficient Canny Edge Detection Using a GPU.
ICNC 2010: 279-280 |
| 20 |  | Yasuaki Ito,
Koji Nakano:
Efficient exhaustive verification of the Collatz conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs.
IPDPS Workshops 2010: 1-8 |
| 19 |  | Yasuaki Ito,
Koji Nakano:
Low-Latency Connected Component Labeling Using an FPGA.
Int. J. Found. Comput. Sci. 21(3): 405-425 (2010) |
| 2009 |
| 18 |  | Yasuaki Ito,
Koji Nakano:
A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Conjecture.
ISPA 2009: 63-70 |
| 17 |  | Masaya Nakagawa,
Duhu Man,
Yasuaki Ito,
Koji Nakano:
A Simple Parallel Convex Hulls Algorithm for Sorted Points and the Performance Evaluation on the Multicore Processors.
PDCAT 2009: 506-511 |
| 16 |  | Duhu Man,
Yasuaki Ito,
Koji Nakano:
An Efficient Parallel Sorting Compatible with the Standard qsort.
PDCAT 2009: 512-517 |
| 2008 |
| 15 |  | Koji Nakano,
Kensuke Kawakami,
Koji Shigemoto,
Yuki Kamada,
Yasuaki Ito:
A Tiny Processing System for Education and Small Embedded Systems on the FPGAs.
EUC (2) 2008: 472-479 |
| 14 |  | Koji Nakano,
Yasuaki Ito:
Processor, Assembler, and Compiler Design Education Using an FPGA.
ICPADS 2008: 723-728 |
| 13 |  | Yasuaki Ito,
Koji Nakano:
Component labeling for k-concave binary images using an FPGA.
IPDPS 2008: 1-8 |
| 12 |  | Yasuaki Ito,
Koji Nakano:
Optimized Component Labeling Algorithm for Using in Medium Sized FPGAs.
PDCAT 2008: 171-176 |
| 11 |  | Yasuaki Ito,
Koji Nakano:
A New FM Screening Method to Generate Cluster-Dot Binary Images Using the Local Exhaustive Search with FPGA Acceleration.
Int. J. Found. Comput. Sci. 19(6): 1373-1386 (2008) |
| 2007 |
| 10 |  | Yasuaki Ito,
Koji Nakano:
Cluster-dot Screening by Local Exhaustive Search with Hardware Accelaration.
IPDPS 2007: 1-8 |
| 9 |  | Yasuaki Ito,
Koji Nakano,
Youhei Yamagishi:
Efficient Hardware Algorithms for n Choose k Counters Using the Bitonic Merger.
Int. J. Found. Comput. Sci. 18(3): 517-528 (2007) |
| 2006 |
| 8 |  | Yasuaki Ito,
Koji Nakano,
Youhei Yamagishi:
Efficient hardware algorithms for n choose k counters.
IPDPS 2006 |
| 7 |  | Jacir Luiz Bordim,
Yasuaki Ito,
Koji Nakano:
Randomized Leader Election Protocols in Noisy Radio Networks with a Single Transceiver.
ISPA 2006: 246-256 |
| 6 |  | Jacir Luiz Bordim,
Yasuaki Ito,
Koji Nakano:
An Energy Efficient Leader Election Protocol for Radio Network with a Single Transceiver.
IEICE Transactions 89-A(5): 1355-1361 (2006) |
| 2005 |
| 5 |  | Yasuaki Ito,
Koji Nakano:
FM Screening By The Local Exhaustive Search, With Hardware Acceleration.
Int. J. Found. Comput. Sci. 16(1): 89-104 (2005) |
| 2004 |
| 4 |  | Yasuaki Ito,
Koji Nakano:
FM Screening by the Local Exhaustive Search, with Hardware Acceleration.
IPDPS 2004 |
| 3 |  | Jacir Luiz Bordim,
Oscar H. Ibarra,
Yasuaki Ito,
Koji Nakano:
Instance-Specific Solutions For Accelerating The Cky Parsing Of Large Context-Free Grammars.
Int. J. Found. Comput. Sci. 15(2): 403-415 (2004) |
| 2003 |
| 2 |  | Jacir Luiz Bordim,
Yasuaki Ito,
Koji Nakano:
Instance-Specific Solutions to Accelerate the CKY Parsing.
Engineering of Reconfigurable Systems and Algorithms 2003: 72-80 |
| 2002 |
| 1 |  | Jacir Luiz Bordim,
Yasuaki Ito,
Koji Nakano:
Accelerating the CKY Parsing Using FPGAs.
HiPC 2002: 41-51 |