Kazuhito Ito

	2012
10		Kazuhito Ito: A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes. IEICE Transactions 95-A(4): 767-775 (2012)
9		Kazuhito Ito, Keisuke Nasu: A Processor Accelerator for Software Decoding of Reed-Solomon Codes. IEICE Transactions 95-A(5): 884-893 (2012)
	2010
8		Kazuhito Ito: A Processor Accelerator for Software Decoding of BCH Codes. IEICE Transactions 93-A(7): 1329-1337 (2010)
	2005
7		Masayuki Masuda, Kazuhito Ito: Rapid and precise instruction set evaluation for application specific processor design. ISCAS (6) 2005: 6210-6213
	2001
6		Tsuyoshi Isshiki, Chawalit Honsawek, Trio Adiono, Kazuhito Ito, Tomohiko Ohtsuka, Dongju Li, Hiroaki Kunieda: H.263+ Video Encoder/Decoder LSI Featuring System-MSPA Architecture and Improved Rate Control Method. ISAS-SCI (1) 2001: 195-200
	2000
5		Kazuhito Ito: A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration. ASP-DAC 2000: 323-328
	1997
4		Kazuhito Ito, Keshab K. Parhi: A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis. VLSI Signal Processing 16(1): 57-72 (1997)
	1995
3		Hiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito: Automatic design for bit-serial MSPA architecture. ASP-DAC 1995
2		Kazuhito Ito, Keshab K. Parhi: Determining the minimum iteration period of an algorithm. VLSI Signal Processing 11(3): 229-244 (1995)
	1994
1		Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi: Module selection and data format conversion for cost-optimal DSP synthesis. ICCAD 1994: 322-329

Coauthor Index

1	Trio Adiono	[6]
2	Chawalit Honsawek	[6]
3	Tsuyoshi Isshiki	[6]
4	Hiroaki Kunieda	[3] [6]
5	Dongju Li	[3] [6]
6	Yusong Liao	[3]
7	Lori E. Lucke	[1]
8	Masayuki Masuda	[7]
9	Keisuke Nasu	[9]
10	Tomohiko Ohtsuka	[6]
11	Keshab K. Parhi	[1] [2] [4]

Colors in the list of coauthors

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