Hideo Ito

	2012
61		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. IEEE Trans. VLSI Syst. 20(5): 804-817 (2012)
	2011
60		Kazuteru Namba, Hideo Ito: Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. IEEE Trans. Computers 60(10): 1459-1470 (2011)
59		Kazuteru Namba, Hideo Ito: Construction of BILBO FF with Soft-Error-Tolerant Capability. IEICE Transactions 94-D(5): 1045-1050 (2011)
	2010
58		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. Asian Test Symposium 2010: 343-348
57		Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito: Quantitative Evaluation of Integrity for Remote System Using the Internet. PRDC 2010: 229-230
56		Kazuteru Namba, Takashi Ikeda, Hideo Ito: Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. IEEE Trans. VLSI Syst. 18(9): 1265-1276 (2010)
55		Kazuteru Namba, Kengo Nakashima, Hideo Ito: Single-Event-Upset Tolerant RS Flip-Flop with Small Area. IEICE Transactions 93-D(12): 3407-3409 (2010)
54		Kazuteru Namba, Hideo Ito: Chiba Scan Delay Fault Testing with Short Test Application Time. J. Electronic Testing 26(6): 667-677 (2010)
	2009
53		Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito: A Delay Measurement Technique Using Signature Registers. Asian Test Symposium 2009: 157-162
52		Takumi Hoshi, Kazuteru Namba, Hideo Ito: Testing of Switch Blocks in Three-Dimensional FPGA. DFT 2009: 227-235
51		Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito: Dependability Evaluation for Internet-Based Remote Systems. PRDC 2009: 256-259
50		Kazuteru Namba, Hideo Ito: Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. IEICE Transactions 92-A(9): 2295-2303 (2009)
49		Kazuteru Namba, Hideo Ito: Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding. IEICE Transactions 92-D(2): 269-282 (2009)
48		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Transactions 92-D(2): 336-341 (2009)
47		Kentaroh Katoh, Kazuteru Namba, Hideo Ito: Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Transactions 92-D(3): 433-442 (2009)
46		Shuangyu Ruan, Kazuteru Namba, Hideo Ito: Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability. IEICE Transactions 92-D(8): 1534-1541 (2009)
45		Kazuteru Namba, Yoshikazu Matsui, Hideo Ito: Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. J. Electronic Testing 25(1): 97-105 (2009)
	2008
44		Shuangyu Ruan, Kazuteru Namba, Hideo Ito: Soft Error Hardened FF Capable of Detecting Wide Error Pulse. DFT 2008: 272-280
43		Kazuteru Namba, Hideo Ito: Delay Fault Testability on Two-Rail Logic Circuits. DFT 2008: 482-490
42		Kazuteru Namba, Hideo Ito: Path Delay Fault Test Set for Two-Rail Logic Circuits. PRDC 2008: 347-348
41		Masato Kitakami, Bochuan Cai, Hideo Ito: A Checkpointing Method with Small Checkpoint Latency. IEICE Transactions 91-D(3): 857-861 (2008)
40		Yoichi Sasaki, Kazuteru Namba, Hideo Ito: Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. J. Electronic Testing 24(1-3): 11-19 (2008)
39		Toshinori Takabatake, Tomoki Nakamigawa, Hideo Ito: Connectivity of Generalized Hierarchical Completely-Connected Networks. Journal of Interconnection Networks 9(1/2): 127-139 (2008)
	2007
38		Takashi Ikeda, Kazuteru Namba, Hideo Ito: Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. DFT 2007: 282-290
37		Abderrahim Doumar, Kentaroh Katoh, Hideo Ito: Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. DFT 2007: 31-40
36		Gang Zeng, Hideo Ito: Low-Cost IP Core Test Using Tri-Template-Based Codes. IEICE Transactions 90-D(1): 288-295 (2007)
	2006
35		Gang Zeng, Hideo Ito: Concurrent core test for SOC using shared test set and scan chain disable. DATE 2006: 1045-1050
34		Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito: Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT 2006: 136-144
33		Yoichi Sasaki, Kazuteru Namba, Hideo Ito: Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. DFT 2006: 327-335
32		Kentaroh Katoh, Hideo Ito: Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. European Test Symposium 2006: 69-74
31		Gang Zeng, Hideo Ito: Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree. IEICE Transactions 89-D(3): 1157-1164 (2006)
30		Kazuteru Namba, Hideo Ito: Proposal of Testable Multi-Context FPGA Architecture. IEICE Transactions 89-D(5): 1687-1693 (2006)
29		Kazuteru Namba, Hideo Ito: Redundant Design for Wallace Multiplier. IEICE Transactions 89-D(9): 2512-2524 (2006)
	2005
28		Gang Zeng, Hideo Ito: Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. ICCD 2005: 143-146
27		Kentaroh Katoh, Abderrahim Doumar, Hideo Ito: Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. IOLTS 2005: 203-204
26		Kazuteru Namba, Hideo Ito: Design of Defect Tolerant Wallace Multiplier. PRDC 2005: 300-304
25		Kazuteru Namba, Hideo Ito: Scan Design for Two-Pattern Test without Extra Latches. IEICE Transactions 88-D(12): 2777-2785 (2005)
24		Gang Zeng, Hideo Ito: Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core. IEICE Transactions 88-D(5): 984-992 (2005)
23		Gang Zeng, Hideo Ito: X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability. IEICE Transactions 88-D(7): 1662-1670 (2005)
22		Kazuteru Namba, Hideo Ito: Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. IEICE Transactions 88-D(9): 2135-2142 (2005)
	2004
21		Gang Zeng, Hideo Ito: Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. DFT 2004: 413-421
20		Manabu Sueishi, Masato Kitakami, Hideo Ito: Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking. PRDC 2004: 183-190
19		Gang Zeng, Hideo Ito: Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. VTS 2004: 355-360
	2003
18		Gang Zeng, Hideo Ito: Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. DFT 2003: 503-510
17		Abderrahim Doumar, Hideo Ito: Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. IEEE Trans. VLSI Syst. 11(3): 386-405 (2003)
	2002
16		Lihong Tong, Kazuki Suzuki, Hideo Ito: Optimal Seed Generation for Delay Fault Detection BIST. Asian Test Symposium 2002: 116-121
15		Toshinori Takabatake, Masato Kitakami, Hideo Ito: A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks. IASTED PDCS 2002: 619-624
14		Toshinori Takabatake, Masato Kitakami, Hideo Ito: Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks. PRDC 2002: 137-144
	2001
13		Toshinori Takabatake, Masato Kitakami, Hideo Ito: Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks. PRDC 2001: 127-136
12		Masato Kitakami, Shunji Kubota, Hideo Ito: Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction. PRDC 2001: 319-324
	2000
11		Abderrahim Doumar, Hideo Ito: Testing approach within FPGA-based fault tolerant systems. Asian Test Symposium 2000: 411-416
10		Abderrahim Doumar, Hideo Ito: Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. DFT 2000: 134-142
	1999
9		Abderrahim Doumar, Hideo Ito: Testing the Logic Cells and Interconnect Resources for FPGAs. Asian Test Symposium 1999: 369-374
8		Abderrahim Doumar, Satoshi Kaneko, Hideo Ito: Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. DFT 1999: 377-385
7		Keiichi Kaneko, Hideo Ito: Fault-Tolerant Routing Algorithms for Hypercube Networks. IPPS/SPDP 1999: 218-224
6		Toshinori Takabatake, Keiichi Kaneko, Hideo Ito: Generalized Hierarchical Completely-Connected Networks. ISPAN 1999: 68-73
5		Mikio Yagi, Keiichi Kaneko, Hideo Ito: LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments. PRDC 1999: 23-
4		Abderrahim Doumar, Hideo Ito: An Automatic Testing and Diagnosis for FPGAs. PRDC 1999: 45-
	1998
3		Hammadi Nait-Charif, Hideo Ito: Improving the Performance of Feedforward Neural Networks by Noise Injection into Hidden Neurons. Journal of Intelligent and Robotic Systems 21(2): 103-115 (1998)
	1994
2		Hideo Ito, Takashi Yagi: Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. DFT 1994: 177-184
	1993
1		Hideo Ito: A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. DFT 1993: 80-87

Coauthor Index

1	Bochuan Cai	[41]
2	Abderrahim Doumar	[4] [8] [9] [10] [11] [17] [27] [37]
3	Takumi Hoshi	[52]
4	Takashi Ikeda	[38] [56]
5	Keiichi Kaneko	[5] [6] [7]
6	Satoshi Kaneko	[8]
7	Akihiro Katada	[51]
8	Kentaroh Katoh	[27] [32] [37] [47] [48] [53] [58] [61]
9	Masato Kitakami	[12] [13] [14] [15] [20] [41] [51] [57]
10	Hiroshi Konno	[57]
11	Shunji Kubota	[12]
12	Yoshikazu Matsui	[45]
13	Hammadi Nait-Charif	[3]
14	Tomoki Nakamigawa	[39]
15	Kengo Nakashima	[55]
16	Kazuteru Namba	[22] [25] [26] [29] [30] [33] [38] [40] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61]
17	Shuangyu Ruan	[44] [46]
18	Yoichi Sasaki	[33] [40]
19	Youhua Shi	[34]
20	Manabu Sueishi	[20]
21	Kazuki Suzuki	[16]
22	Toshinori Takabatake	[6] [13] [14] [15] [34] [39]
23	Toru Tanabe	[53]
24	Lihong Tong	[16]
25	Mikio Yagi	[5]
26	Takashi Yagi	[2]
27	Masao Yanagisawa	[34]
28	Haque Md Zahidul	[53]
29	Gang Zeng	[18] [19] [21] [23] [24] [28] [31] [34] [35] [36]

Colors in the list of coauthors

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page