Alexander T. Ishii

	2012
3		Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger: Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC 2012: 68-70
	1997
2		Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou: Optimizing two-phase, level-clocked circuitry. J. ACM 44(1): 148-199 (1997)
	1993
1		Alexander T. Ishii: Retiming gated-clocks and precharged circuit structures. ICCAD 1993: 300-307

Coauthor Index

1	Srikanth Arekapudi	[3]
2	Charles E. Leiserson	[2]
3	Samuel Naffziger	[3]
4	Charles Ouyang	[3]
5	Marios C. Papaefthymiou	[2] [3]
6	Visvesh S. Sathe	[3]

Last update Fri Jun 1 15:44:53 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page