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Koichiro Ishibashi Coauthor index pubzone.org

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DBLP keys2012
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Transactions 95-C(4): 643-650 (2012)
2011
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS 2011: 111-114
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC 2011: 183-186
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Transactions 94-C(4): 511-519 (2011)
2010
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi: A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. J. Solid-State Circuits 45(11): 2312-2320 (2010)
2007
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYoshihide Komatsu, Koichiro Ishibashi, Makoto Nagata: Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. IEICE Transactions 90-C(4): 692-698 (2007)
2006
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada: Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Transactions 89-C(3): 250-262 (2006)
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYoshihide Komatsu, Yukio Arima, Koichiro Ishibashi: Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond. IEICE Transactions 89-C(3): 384-391 (2006)
2005
6no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara: Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD 2005: 398-405
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTakahiro Yamashita, Tetsuya Fujimoto, Koichiro Ishibashi: Power Valve: for low power operation and low stand-by power. IEICE Electronic Express 2(3): 64-69 (2005)
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKoichiro Ishibashi: Special Section on Low-Power LSI and Low-Power IP. IEICE Transactions 88-C(4): 467 (2005)
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai: Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Systems and Computers in Japan 36(6): 39-48 (2005)
1999
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHiroyuki Mizuno, Koichiro Ishibashi: A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. IEEE Trans. VLSI Syst. 7(1): 139-144 (1999)
1998
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMasayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi: A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. ISLPED 1998: 48-53

Coauthor Index

1Kazuo Aisaka [3]
2Yukio Arima [7] [8]
3Toshiyuki Aritsuka [3]
4Kunihiro Asada [11] [12] [13] [14]
5Tetsuya Fujimoto [5] [8]
6Masato Hagiwara [8]
7Yasuyuki Hashimoto [8]
8Motoi Ichihashi [8]
9Makoto Ikeda [11] [12] [13] [14]
10Susumu Imaoka [6]
11Yasuo Itoh [8]
12Yusuke Kanno [10]
13Hiroshi Kawaguchi [3]
14Jinmyoung Kim [11] [12] [13] [14]
15Shigenobu Komatsu [10]
16Yoshihide Komatsu [7] [8] [9]
17Hiroshi Makino [6]
18Isao Minematsu [8]
19Satoshi Misaka [3]
20Masayuki Miyazaki [1]
21Hiroyuki Mizuno [1] [2]
22Makoto Nagata [9]
23Toru Nakura [11] [12] [13] [14]
24Koji Nii [6]
25Yuji Oda [6]
26Shigeki Ohbayashi [6]
27Hiroyuki Okada [8]
28Masafumi Onouchi [10]
29Makoto Saen [10]
30Kohji Sakata [8]
31Takayasu Sakurai [3]
32Hirofumi Shinohara [6]
33Hidehiro Takata [11] [12] [13] [14]
34Haruki Toda [8]
35Keisuke Toyama [3]
36Toshiro Tsukada [8]
37Yasumasa Tsukamoto [6]
38Kunio Uchiyama [3]
39Takahiro Yamashita [5] [8]
40Yoshihiko Yasu [10]
41Tomoaki Yoshizawa [6]

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