Michiko Inoue

	2011
48		Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara: Temperature-Variation-Aware Test Pattern Optimization. European Test Symposium 2011: 214
47		Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara: Faster-than-at-speed test for increased test quality and in-field reliability. ITC 2011: 1-9
46		Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara: Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electronic Testing 27(2): 99-108 (2011)
	2010
45		Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium 2010: 206-211
44		Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara: Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium 2010: 313-318
43		Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara: Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. Asian Test Symposium 2010: 371-374
42		Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara: Test pattern selection to optimize delay test quality with a limited size of test set. European Test Symposium 2010: 260
41		Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara: Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS 2010: 21-26
40		Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara: Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS 2010: 188-193
	2009
39		Michiko Inoue, Tsuyoshi Suzuki, Hideo Fujiwara: Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. DISC 2009: 172-173
38		Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara: Partial Scan Approach for Secret Information Protection. European Test Symposium 2009: 143-148
	2008
37		Seiji Kajihara, Michiko Inoue: Special Section on Test and Verification of VLSIs. IEICE Transactions 91-D(3): 640-641 (2008)
36		Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara: Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Transactions 91-D(3): 763-770 (2008)
	2006
35		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. VLSI Syst. 14(11): 1203-1215 (2006)
34		Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara: A Low Power Deterministic Test Using Scan Chain Disable Technique. IEICE Transactions 89-D(6): 1931-1939 (2006)
	2005
33		Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Asian Test Symposium 2005: 254-259
32		Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki: Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. Asian Test Symposium 2005: 444-449
31		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Testing Superscalar Processors in Functional Mode. FPL 2005: 747-750
30		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-based delay fault self-testing of pipelined processor cores. ISCAS (6) 2005: 5686-5689
29		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Delay Fault Testing of Processor Cores in Functional Mode. IEICE Transactions 88-D(3): 610-618 (2005)
28		Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara: Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. IEICE Transactions 88-D(8): 1940-1947 (2005)
	2004
27		Kazuko Kambe, Michiko Inoue, Hideo Fujiwara: Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. Asian Test Symposium 2004: 152-157
26		Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara: Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. Asian Test Symposium 2004: 32-39
25		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Delay Fault Self-Testing of Processor Cores. VLSI Design 2004: 933-
	2003
24		Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara: Test Synthesis for Datapaths Using Datapath-Controller Functions. Asian Test Symposium 2003: 294-299
23		Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Software-Based Delay Fault Testing of Processor Cores. Asian Test Symposium 2003: 68-71
	2002
22		Michiko Inoue, Chikateru Jinno, Hideo Fujiwara: An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. ICCD 2002: 200-205
21		Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. J. Electronic Testing 18(1): 55-62 (2002)
20		Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Parallel algorithms for selection on the BSP and BSP* models. Systems and Computers in Japan 33(12): 97-107 (2002)
19		Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A layout adjustment problem for disjoint rectangles preserving orthogonal order. Systems and Computers in Japan 33(2): 31-42 (2002)
	2001
18		Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa, Hideo Fujiwara: Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps. DISC 2001: 123-135
17		Chikara Ohori, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A causal broadcast protocol for distributed mobile systems. Systems and Computers in Japan 32(3): 65-75 (2001)
	2000
16		Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: A class of sequential circuits with combinational test generation complexity under single-fault assumption. Asian Test Symposium 2000: 398-403
15		Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa: Parallelizability of Some P-Complete Problems. IPDPS Workshops 2000: 116-122
	1999
14		Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. Asian Test Symposium 1999: 5-12
13		Akihiro Fujiwara, H. Katsuki, Michiko Inoue, Toshimitsu Masuzawa: Parallel Selection Algorithms with Analysis on Clusters. ISPAN 1999: 388-393
12		Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model. ISPAN 1999: 394-399
11		Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A cost optimal parallel algorithm for weighted distance transforms. Parallel Computing 25(4): 405-416 (1999)
	1998
10		Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara: A High-Level Synthesis Method for Weakly Testable Data Paths. Asian Test Symposium 1998: 40-45
9		Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order. Graph Drawing 1998: 183-197
8		Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: SelfStabilizing WaitFree Clock Synchronization with Bounded Space. OPODIS 1998: 129-144
7		Michiko Inoue, Hideo Fujiwara: An approach to test synthesis from higher level. Integration 26(1-2): 101-116 (1998)
	1997
6		Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Parallel Algorithm for Weighted Distance Transforms. IPPS 1997: 407-412
5		Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara: Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System. WDAG 1997: 290-304
4		Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Non-scan design for testable data paths using thru operation. Systems and Computers in Japan 28(10): 60-68 (1997)
	1996
3		Yasuo Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Snapshot Algorithm for Distributed Mobile Systems. ICDCS 1996: 734-743
	1994
2		Michiko Inoue, Wei Chen: Linear-Time Snapshot Using Multi-writer Multi-reader Registers. WDAG 1994: 130-140
	1992
1		T. Yamada, Akihiro Fujiwara, Michiko Inoue: COM (Cost Oriented Memory) Testing. ITC 1992: 259

Coauthor Index

1	Wei Chen	[2]
2	Akihiro Fujiwara	[1] [6] [11] [12] [13] [15] [20]
3	Hideo Fujiwara	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48]
4	Emil Gizdarski	[16] [21]
5	Muneo Hasegawa	[38] [46]
6	Kunihiko Hayashi	[9] [19]
7	Takeshi Higashimura	[10]
8	Keigo Hori	[47]
9	Jiedi Huang	[43]
10	Takashi Ishimizu	[12] [20]
11	Tsuyoshi Iwagaki	[32] [34]
12	Hiroshi Iwata	[42] [45]
13	Chikateru Jinno	[22]
14	Seiji Kajihara	[37] [41]
15	Kazuko Kambe	[27] [32]
16	H. Katsuki	[13]
17	Jishun Kuang	[43]
18	Toshimitsu Masuzawa	[3] [4] [5] [6] [8] [9] [10] [11] [12] [13] [15] [17] [18] [19] [20]
19	Sen Moriya	[5] [8]
20	Makoto Nakao	[48]
21	Masato Nakasato	[36]
22	Kenji Noda	[10]
23	Chikara Ohori	[17]
24	Satoshi Ohtake	[14] [33] [36] [45]
25	Hiroyuki Okamoto	[24]
26	Kewal K. Saluja	[23] [25] [29] [30] [31] [35]
27	Yasuo Sato	[3] [40] [41] [48]
28	Jacob Savir	[26] [28]
29	Virendra Singh	[23] [25] [29] [30] [31] [35]
30	Kazuhiro Suzuki	[24]
31	Tsuyoshi Suzuki	[39]
32	Katsuyuki Takabatake	[4]
33	Akira Taketani	[42] [44]
34	Shinya Umetani	[18]
35	T. Yamada	[1]
36	Ken-ichi Yamaguchi	[26] [28]
37	Hyunbean Yi	[41]
38	Tomokazu Yoneda	[38] [40] [41] [42] [44] [46] [47] [48]
39	Yuki Yoshikawa	[33]
40	Zhiqiang You	[26] [28] [34] [43]

Colors in the list of coauthors

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