 | 2012 |
| 23 |  | Keisuke Inoue,
Mineo Kaneko:
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis.
ACM Great Lakes Symposium on VLSI 2012: 79-82 |
| 22 |  | Keisuke Inoue,
Mineo Kaneko:
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range.
ASP-DAC 2012: 239-244 |
| 21 |  | Keisuke Inoue,
Mineo Kaneko:
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis.
ISQED 2012: 778-783 |
| 2011 |
| 20 |  | Mineo Kaneko,
Keisuke Inoue:
Ordered coloring-based resource binding for datapaths with improved skew-adjustability.
ACM Great Lakes Symposium on VLSI 2011: 307-312 |
| 19 |  | Keisuke Inoue,
Mineo Kaneko:
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis.
ISCAS 2011: 550-553 |
| 18 |  | Keisuke Inoue,
Mineo Kaneko:
Early planning for RT-level delay insertion during clock skew-aware register binding.
VLSI-SoC 2011: 154-159 |
| 17 |  | Keisuke Inoue,
Mineo Kaneko,
Tsuyoshi Iwagaki:
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis.
IEICE Transactions 94-A(4): 1067-1081 (2011) |
| 2010 |
| 16 |  | Keisuke Inoue,
Mineo Kaneko:
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths.
ACM Great Lakes Symposium on VLSI 2010: 111-114 |
| 2009 |
| 15 |  | Keisuke Inoue,
Mineo Kaneko,
Tsuyoshi Iwagaki:
Safe clocking for the setup and hold timing constraints in datapath synthesis.
ACM Great Lakes Symposium on VLSI 2009: 27-32 |
| 14 |  | Keisuke Inoue,
Mineo Kaneko,
Tsuyoshi Iwagaki:
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths.
IEICE Transactions 92-A(4): 1096-1105 (2009) |
| 2008 |
| 13 |  | Ebru Arisoy,
Keisuke Inoue,
Wolfgang Maier:
ACL 2008, Proceedings of the 46th Annual Meeting of the Association for Computational Linguistics, June 15-20, 2008, Columbus, Ohio, USA, Student Research Workshop
The Association for Computer Linguistics 2008 |
| 12 |  | Keisuke Inoue,
Mineo Kaneko,
Tsuyoshi Iwagaki:
Safe clocking register assignment in datapath synthesis.
ICCD 2008: 120-127 |
| 11 |  | Keisuke Inoue,
Mineo Kaneko,
Tsuyoshi Iwagaki:
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation.
IEICE Transactions 91-A(4): 1044-1053 (2008) |
| 2006 |
| 10 |  | James Howison,
Keisuke Inoue,
Kevin Crowston:
Social dynamics of free and open source team communications.
OSS 2006: 319-330 |
| 2005 |
| 9 |  | Tsuyoshi Idé,
Keisuke Inoue:
Knowledge Discovery from Heterogeneous Dynamic Systems using Change-Point Correlations.
SDM 2005 |
| 2001 |
| 8 |  | Keisuke Inoue,
Takayuki Itoh,
Atsushi Yamada,
Tomotake Furuhata,
Kenji Shimada:
Face clustering of a large-scale CAD model for surface mesh generation.
Computer-Aided Design 33(3): 251-261 (2001) |
| 2000 |
| 7 |  | Atsushi Yamada,
Keisuke Inoue,
Takayuki Itoh,
Kenji Shimada:
An Approach for Generating Meshes Similar to A Reference Mesh.
IMR 2000: 101-109 |
| 1999 |
| 6 |  | Masaki Wakabayashi,
Keisuke Inoue,
Hideharu Amano:
ISIS: Multiprocessor Simulator Library.
Applied Informatics 1999: 198-200 |
| 5 |  | Keisuke Inoue,
Takayuki Itoh,
Atsushi Yamada,
Tomotake Furuhata,
Kenji Shimada:
Clustering Large Number of Faces for 2-Dimensional Mesh Generation.
IMR 1999: 281-292 |
| 1998 |
| 4 |  | Takayuki Itoh,
Kenji Shimada,
Keisuke Inoue,
Atsushi Yamada,
Tomotake Furuhata:
Automated Conversion of 2D Triangular Mesh into Quadrilateral Mesh with Directionality Control.
IMR 1998: 77-86 |
| 1997 |
| 3 |  | Toru Kisuki,
Masaki Wakabayashi,
Junji Yamamoto,
Keisuke Inoue,
Hideharu Amano:
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors.
Euro-Par 1997: 793-797 |
| 2 |  | Takuya Terasawa,
Keisuke Inoue,
Hitoshi Kurosawa,
Hideharu Amano:
A study on snoop cache systems for single-chip multiprocessors.
Systems and Computers in Japan 28(2): 62-72 (1997) |
| 1996 |
| 1 |  | Keisuke Inoue,
Toru Kisuki,
Michitaka Okuno,
Etsuko Shimizu,
Takuya Terasawa,
Hideharu Amano:
ATTEMPT-1: A Reconfigurable Multiprocessor Testbed.
FPL 1996: 200-209 |