 | 2012 |
|---|
| 6 |       | Kazuki Inoue,
Masahiro Koga,
Motoki Amagasaki,
Masahiro Iida,
Yoshinobu Ichida,
Mitsuro Saji,
Jun Iida,
Toshinori Sueyoshi:
An Easily Testable Routing Architecture and Prototype Chip.
IEICE Transactions 95-D(2): 303-313 (2012) |
| 2011 |
|---|
| 5 | | Kazuki Inoue,
Hiroki Yosho,
Motoki Amagasaki,
Masahiro Iida,
Toshinori Sueyoshi:
An Easily Testable Routing Architecture and Efficient Test Technique.
FPL 2011: 291-294 |
| 4 | | Masahiro Iida,
Kazuki Inoue,
Motoki Amagasaki,
Toshinori Sueyoshi:
An easily testable routing architecture of FPGA.
VLSI-SoC 2011: 106-109 |
| 3 | | Masahiro Iida,
Masahiro Koga,
Kazuki Inoue,
Motoki Amagasaki,
Yoshinobu Ichida,
Mitsuro Saji,
Jun Iida,
Toshinori Sueyoshi:
A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.
IEICE Transactions 94-C(4): 548-556 (2011) |
| 2010 |
|---|
| 2 | | Kazuki Inoue,
Qian Zhao,
Yasuhiro Okamoto,
Hiroki Yosho,
Motoki Amagasaki,
Masahiro Iida,
Toshinori Sueyoshi:
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core.
TRETS 4(1): 5 (2010) |
| 2009 |
|---|
| 1 | | Kazuki Inoue,
Motoki Amagasaki,
Masahiro Iida,
Toshinori Sueyoshi:
A Novel Local Interconnect Architecture for Variable Grain Logic Cell.
ARC 2009: 97-109 |
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