Hiroshi Inokawa

	2012
9		Mingu Jo, Yuki Kato, Masashi Arita, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Yasuo Takahashi, Jung-Bum Choi: Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device. IEICE Transactions 95-C(5): 865-870 (2012)
	2009
8		Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi: Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs. IJNMC 1(2): 58-69 (2009)
	2007
7		Wancheng Zhang, Katsuhiko Nishiguchi, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi, Hiroshi Inokawa, Yasuo Takahashi, Nan-Jian Wu: Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors. IEICE Transactions 90-C(5): 943-948 (2007)
6		Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi: Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. Multiple-Valued Logic and Soft Computing 13(3): 249-266 (2007)
	2006
5		Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi: A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2006: 19
	2005
4		Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi: A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2005: 32-38
	2004
3		Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi: A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. ISMVL 2004: 262-268
2		Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi: A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ISMVL 2004: 269-274
	2003
1		Hiroshi Inokawa, Yasuo Takahashi: Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic. ISMVL 2003: 259-266

Coauthor Index

1	Takafumi Aoki	[2] [3] [4] [5] [6]
2	Masashi Arita	[8] [9]
3	Jung-Bum Choi	[9]
4	Katsuhiko Degawa	[2] [3] [4] [5] [6]
5	Akira Fujiwara	[7] [8] [9]
6	Tatsuo Higuchi	[2] [3] [4] [5] [6]
7	Mingu Jo	[9]
8	Mingyu Jo	[8]
9	Takuya Kaizawa	[8]
10	Yuki Kato	[9]
11	Katsuhiko Nishiguchi	[5] [7]
12	Yukinori Ono	[7] [8] [9]
13	Yasuo Takahashi	[1] [2] [3] [4] [5] [6] [7] [8] [9]
14	Nan-Jian Wu	[7]
15	Hiroshi Yamaguchi	[7]
16	Kenji Yamazaki	[8]
17	Wancheng Zhang	[7]

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