Masato Inagi

	2012
7		Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro: A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. IEICE Transactions 95-D(2): 324-334 (2012)
	2011
6		Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama: An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators. FPL 2011: 157-161
5		Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro: EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. ReConFig 2011: 448-454
	2009
4		Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura: Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. FPL 2009: 212-217
	2008
3		Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi: ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. ISCAS 2008: 1800-1803
2		Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi: Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. IEICE Transactions 91-A(12): 3539-3547 (2008)
	2007
1		Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani: A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Transactions 90-A(5): 924-931 (2007)

Coauthor Index

1	Tetsuo Hironaka	[5] [7]
2	Takashi Ishiguro	[5] [7]
3	Yoji Kajitani	[1]
4	Shinobu Nagayama	[6]
5	Masatoshi Nakamura	[5] [7]
6	Yuichi Nakamura (Yuhichi Nakamura)	[1] [2] [3] [4]
7	Masayuki Sato	[5] [7]
8	Atsushi Takahashi	[2] [3]
9	Yasuhiro Takashima	[1] [2] [3] [4]
10	Kazuya Tanigawa	[5] [7]
11	Yoichi Wakaba	[6]
12	Shin'ichi Wakabayashi	[6]

Colors in the list of coauthors

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page