Motoi Inaba

	2010
7		Motoi Inaba, Koichi Tanno, Hiroki Tamura, Okihiko Ishizuka: Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits. IEICE Transactions 93-D(8): 2073-2079 (2010)
	2009
6		Motoi Inaba, Koichi Tanno, Ryota Sawada, Hisashi Tanaka, Hiroki Tamura: Optimization of Current-Mode MVD-ORNS Arithmetic Circuits. ISMVL 2009: 42-47
	2007
5		Motoi Inaba: Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process. ISMVL 2007: 58
	2006
4		Muneo Kushima, Motoi Inaba, Koichi Tanno: Linear and Compact Floating Node Voltage-Controlled Variable Resistor Circuit. IEICE Transactions 89-A(2): 459-460 (2006)
	2002
3		Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. ISMVL 2002: 282-
	2001
2		Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators. ISMVL 2001: 27-
	2000
1		Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. ISMVL 2000: 15-20

Coauthor Index

1	Okihiko Ishizuka	[1] [2] [3] [7]
2	Muneo Kushima	[4]
3	Ryota Sawada	[6]
4	Jing Shen	[1]
5	Hiroki Tamura	[6] [7]
6	Hisashi Tanaka	[6]
7	Koichi Tanno	[1] [2] [3] [4] [6] [7]

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