 | 2011 |
|---|
| 8 |       | José Luis Imaña:
Low Latency GF(2m) Polynomial Basis Multiplier.
IEEE Trans. on Circuits and Systems 58-I(5): 935-946 (2011) |
| 2010 |
|---|
| 7 | | Gustavo Sutter,
Jean-Pierre Deschamps,
José Luis Imaña:
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation.
FPL 2010: 496-501 |
| 6 | | José Luis Imaña:
Probabilistic Verification over GF(2m) Using Mod2-OBDDs.
Intelligent Information Management 2(2): 95-103 (2010) |
| 2008 |
|---|
| 5 |  | Joachim von zur Gathen,
José Luis Imaña,
Çetin Kaya Koç:
Arithmetic of Finite Fields, 2nd International Workshop, WAIFI 2008, Siena, Italy, July 6-9, 2008, Proceedings
Springer 2008 |
| 2006 |
|---|
| 4 | | José Luis Imaña,
Juan Manuel Sánchez,
Francisco Tirado:
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials.
IEEE Trans. Computers 55(5): 520-533 (2006) |
| 3 | | José Luis Imaña,
Román Hermida,
Francisco Tirado:
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.
IEEE Trans. VLSI Syst. 14(12): 1388-1393 (2006) |
| 2 | | José Luis Imaña,
Juan Manuel Sánchez:
Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF(2m) Generated by AOPs.
VLSI Signal Processing 42(3): 285-296 (2006) |
| 2003 |
|---|
| 1 | | José Luis Imaña,
Juan Manuel Sánchez:
A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2m).
FPL 2003: 1127-1130 |
Data released under the ODC-BY 1.0 license — See also our legal information page