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| 2012 | ||
|---|---|---|
| 141 | Elis Kulla, Makoto Ikeda, Tetsuya Oda, Leonard Barolli, Fatos Xhafa, Aleksander Biberaj: Evaluation of a MANET Testbed in Outdoor Bridge Environment Using BATMAN Routing Protocol. AINA 2012: 384-390 | |
| 140 | Makoto Ikeda, Elis Kulla, Masahiro Hiyama, Leonard Barolli, Makoto Takizawa: Impact of Multi-flow Traffic in Wireless Mobile Ad-hoc Networks. AINA 2012: 621-628 | |
| 139 | Evjola Spaho, Makoto Ikeda, Leonard Barolli, Fatos Xhafa, Aleksander Biberaj, Jiro Iwashige: Performance Comparison of DSDV and DYMO Protocols for Vehicular Ad Hoc Networks. AINA 2012: 629-634 | |
| 138 | Masahiro Hiyama, Elis Kulla, Tetsuya Oda, Makoto Ikeda, Leonard Barolli: Experimental Results of a MANET Testbed in a Mixed Environment Considering Horizontal and Vertical Topologies. AINA 2012: 884-889 | |
| 137 | James S. Tandon, Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada: A design-for-test apparatus for measuring on-chip temperature with fine granularity. ISQED 2012: 27-32 | |
| 136 | Makoto Ikeda, Albert Theuwissen, Johannes Solhusvik, Jan Bosiers, Makoto Ikeda: Computational imaging. ISSCC 2012: 504-505 | |
| 135 | Makoto Ikeda, Albert Theuwissen, Johannes Solhusvik, Jan Bosiers, Makoto Ikeda: Computational imaging. ISSCC 2012: 504-505 | |
| 134 | Elis Kulla, Masahiro Hiyama, Makoto Ikeda, Leonard Barolli: Performance comparison of OLSR and BATMAN routing protocols by a MANET testbed in stairs environment. Computers & Mathematics with Applications 63(2): 339-349 (2012) | |
| 133 | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. IEICE Transactions 95-C(4): 546-554 (2012) | |
| 132 | Hiroki Yabe, Makoto Ikeda: 3-D Range Map Acquisition System Based on CMOS Image Sensor Using Time-Multiplexing Structured Pattern. IEICE Transactions 95-C(4): 635-642 (2012) | |
| 131 | Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. IEICE Transactions 95-C(4): 643-650 (2012) | |
| 130 | Ailixier Aikebaier, Makoto Takizawa, Isamu Tsuneizumi, Makoto Ikeda, Tomoya Enokido: A multi-layered model for scalable group communication with hybrid clocks. Int. J. Pervasive Computing and Communications 8(1): 79-91 (2012) | |
| 129 | Tetsuya Oda, Admir Barolli, Fatos Xhafa, Leonard Barolli, Makoto Ikeda, Makoto Takizawa: Performance evaluation of WMN-GA for different mutation and crossover rates considering number of covered users parameter. Mobile Information Systems 8(1): 1-16 (2012) | |
| 2011 | ||
| 128 | Soichi Sawamura, Admir Barolli, Ailixier Aikebaier, Makoto Ikeda, Makoto Takizawa: Objective Trustworthiness of Acquaintances in Peer-to-Peer (P2P) Overlay Networks. AINA 2011: 167-174 | |
| 127 | Isamu Tsuneizumi, Ailixier Aikebaier, Makoto Ikeda, Tomoya Enokido, Makoto Takizawa: A Multi-layered Model for Scalable Group Communication in P2P Overlay Networks. AINA 2011: 324-331 | |
| 126 | Makoto Ikeda, Elis Kulla, Masahiro Hiyama, Leonard Barolli, Makoto Takizawa: Experimental Results of a MANET Testbed in Indoor Stairs Environment. AINA 2011: 779-786 | |
| 125 | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC 2011: 75-76 | |
| 124 | Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC 2011: 79-80 | |
| 123 | Elis Kulla, Makoto Ikeda, Masahiro Hiyama, Leonard Barolli, Rozeta Miho: Performance Evaluation of OLSR and BATMAN Protocols for Vertical Topology Using Indoor Stairs Testbed. BWCCA 2011: 159-166 | |
| 122 | Makoto Ikeda, Masahiro Hiyama, Elis Kulla, Leonard Barolli, Makoto Takizawa: Multi-hop Wireless Networks Performance Evaluation via NS-3 Simulator. BWCCA 2011: 243-249 | |
| 121 | Masahiro Hiyama, Elis Kulla, Makoto Ikeda, Leonard Barolli: Investigation of Channel Usage and Packetloss in a MANET Testbed for Stairs Indoor Scenarios. BWCCA 2011: 499-504 | |
| 120 | Elis Kulla, Makoto Ikeda, Masahiro Hiyama, Leonard Barolli: Evaluation of a MANET Testbed in Indoor Stairs Environment Considering OLSR Protocol. CISIS 2011: 160-167 | |
| 119 | Tadateru Ohkawara, Ailixier Aikebaier, Makoto Ikeda, Tomoya Enokido, Makoto Takizawa: Quorum-based Synchronization Protocol of Object Replicas in Scalable Distributed Systems. CISIS 2011: 391-396 | |
| 118 | Makoto Ikeda, Elis Kulla, Leonard Barolli, Makoto Takizawa: Wireless Ad-hoc Networks Performance Evaluation Using NS-2 and NS-3 Network Simulators. CISIS 2011: 40-45 | |
| 117 | Masahiro Hiyama, Elis Kulla, Makoto Ikeda, Leonard Barolli: Performance Evaluation of a MANET Testbed for Different Indoor Scenarios: A Comparison Study. CISIS 2011: 420-425 | |
| 116 | Isamu Tsuneizumi, Ailixier Aikebaier, Makoto Ikeda, Tomoya Enokido, Makoto Takizawa: A Scalable Communication Protocol for Multi-layered Groups. CISIS 2011: 426-431 | |
| 115 | Takuro Inoue, Makoto Ikeda, Tomoya Enokido, Ailixier Aikebaier, Makoto Takizawa: A Power Consumption Model for Storage-based Applications. CISIS 2011: 612-617 | |
| 114 | Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: Decoupling capacitance boosting for on-chip resonant supply noise reduction. DDECS 2011: 111-114 | |
| 113 | Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. ESSCIRC 2011: 183-186 | |
| 112 | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system. ICECS 2011: 53-56 | |
| 111 | Sanad Bushnaq, Makoto Ikeda, Kunihiro Asada: All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS. ICECS 2011: 607-610 | |
| 110 | Elis Kulla, Masahiro Hiyama, Makoto Ikeda, Leonard Barolli: Comparison of Experimental Results of a MANET Testbed in Different Environments Considering BATMAN Protocol. INCoS 2011: 1-7 | |
| 109 | Makoto Ikeda, Masahiro Hiyama, Elis Kulla, Leonard Barolli: Mobile Ad-hoc Network Routing Protocols Performance Evaluation Using NS-3 Simulator. INCoS 2011: 14-20 | |
| 108 | Masahiro Hiyama, Elis Kulla, Makoto Ikeda, Leonard Barolli, Jiro Iwashige: Performance Evaluation of MANET Testbed in a Mixed Indoor and Outdoor Environment. INCoS 2011: 771-776 | |
| 107 | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. ISLPED 2011: 3-8 | |
| 106 | Makoto Ikeda, Elis Kulla, Leonard Barolli, Makoto Takizawa, Rozeta Miho: Performance Evaluation of Wireless Mobile Ad-Hoc Network via NS-3 Simulator. NBiS 2011: 135-141 | |
| 105 | Elis Kulla, Makoto Ikeda, Masahiro Hiyama, Leonard Barolli, Bexhet Kamo: Real Data from a Testbed in Indoor Stairs Environment Considering BATMAN Protocol. NBiS 2011: 35-41 | |
| 104 | Isamu Tsuneizumi, Ailixier Aikebaier, Makoto Ikeda, Tomoya Enokido, Makoto Takizawa: A scalable group communication protocol with hybrid clocks. Concurrency and Computation: Practice and Experience 23(5): 477-490 (2011) | |
| 103 | Makoto Ikeda, Fumio Arakawa: Cool Chips. IEEE Micro 31(6): 4-5 (2011) | |
| 102 | Shingo Mandai, Taihei Momma, Makoto Ikeda, Kunihiro Asada: Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method. IEICE Transactions 94-C(1): 124-127 (2011) | |
| 101 | Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Transactions 94-C(4): 487-494 (2011) | |
| 100 | Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada: On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. IEICE Transactions 94-C(4): 511-519 (2011) | |
| 99 | Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Transactions 94-C(4): 654-662 (2011) | |
| 98 | Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada: 1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Transactions 94-C(6): 1098-1104 (2011) | |
| 97 | Isamu Tsuneizumi, Ailixier Aikebaier, Makoto Ikeda, Tomoya Enokido, Makoto Takizawa: Design and Implementation of Hybrid Time (HT) Group Communication Protocol for Homogeneous Broadcast Groups. IJDST 2(3): 37-48 (2011) | |
| 96 | Tao Yang, Gjergji Mino, Leonard Barolli, Makoto Ikeda, Fatos Xhafa, Arjan Durresi: Performance of Wireless Sensor Networks for Different Mobile Event Path Scenarios. IJDST 2(3): 49-63 (2011) | |
| 95 | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada: A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. J. Solid-State Circuits 46(11): 2500-2513 (2011) | |
| 2010 | ||
| 94 | Makoto Ikeda, Masahiro Hiyama, Leonard Barolli, Fatos Xhafa, Arjan Durresi, Makoto Takizawa: Mobility Effects of Wireless Multi-hop Networks in Indoor Scenarios. AINA 2010: 495-502 | |
| 93 | Tao Yang, Makoto Ikeda, Gjergji Mino, Leonard Barolli, Arjan Durresi, Fatos Xhafa: Performance Evaluation of Wireless Sensor Networks for Mobile Sink Considering Consumed Energy Metric. AINA Workshops 2010: 245-250 | |
| 92 | Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Cascaded time difference amplifier using differential logic delay cell. ASP-DAC 2010: 355-356 | |
| 91 | Isamu Tsuneizumi, Ailixier Aikebaier, Makoto Ikeda, Tomoya Enokido, Makoto Takizawa: A Scalable Hybrid Time Protocol for a Heterogeneous Group. BWCCA 2010: 214-221 | |
| 90 | Masahiro Hiyama, Makoto Ikeda, Leonard Barolli, Elis Kulla, Fatos Xhafa, Arjan Durresi: Experimental Evaluation of a MANET Testbed in Indoor Stairs Scenarios. BWCCA 2010: 678-683 | |
| 89 | Makoto Ikeda, Elis Kulla, Masahiro Hiyama, Leonard Barolli, Makoto Takizawa: Analysis of MANET Routing Protocols for Indoor Environment. BWCCA 2010: 9-16 | |
| 88 | Elis Kulla, Makoto Ikeda, Leonard Barolli, Rozeta Miho: Impact of Source and Destination Movement on MANET Performance Considering BATMAN and AODV Protocols. BWCCA 2010: 94-101 | |
| 87 | Tao Yang, Makoto Ikeda, Leonard Barolli, Arjan Durresi, Fatos Xhafa: Performance Evaluation of Wireless Sensor Networks for Different Radio Models Considering Mobile Event. CISIS 2010: 180-187 | |
| 86 | Makoto Ikeda, Masahiro Hiyama, Leonard Barolli, Fatos Xhafa, Arjan Durresi: Mobility Effects on the Performance of Mobile Ad hoc Networks. CISIS 2010: 230-237 | |
| 85 | Shingo Mandai, Makoto Ikeda, Kunihiro Asada: A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary. ISSCC 2010: 404-405 | |
| 84 | Johannes Solhusvik, Jung-Chak Ahn, Jan Bosiers, Boyd Fowler, Makoto Ikeda, Shoji Kawahito, Jerry Lin, Dan McGrath, Katsu Nakamura, Jun Ohta, Ramchan Woo: High-speed image sensor technologies. ISSCC 2010: 516-517 | |
| 83 | Isamu Tsuneizumi, Ailixier Aikebaier, Makoto Ikeda, Tomoya Enokido, Makoto Takizawa, S. Misbah Deen: A two-layered model for scalable, heterogeneous group communications. MoMM 2010: 126-131 | |
| 82 | Isamu Tsuneizumi, Ailixier Aikebaier, Makoto Ikeda, Tomoya Enokido, Makoto Takizawa, S. Misbah Deen: Hybrid Clock-Based Synchronization in a Scalable Heterogeneous Group. NBiS 2010: 246-253 | |
| 81 | Makoto Ikeda, Elis Kulla, Masahiro Hiyama, Leonard Barolli, Makoto Takizawa, Rozeta Miho: A Comparison Study between Simulation and Experimental Results for MANETs. NBiS 2010: 371-378 | |
| 80 | Elis Kulla, Makoto Ikeda, Leonard Barolli, Rozeta Miho, Vladi Kolici: Effects of Source and Destination Movement on MANET Performance Considering OLSR and AODV Protocols. NBiS 2010: 510-515 | |
| 79 | Leonard Barolli, Makoto Ikeda, Fatos Xhafa, Arjan Durresi: A Testbed for MANETs: Implementation, Experiences and Learned Lessons. IEEE Systems Journal 4(2): 243-252 (2010) | |
| 78 | Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada: A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Transactions 93-A(7): 1319-1328 (2010) | |
| 77 | Toru Nakura, Shingo Mandai, Makoto Ikeda, Kunihiro Asada: Time Difference Amplifier with Robust Gain Using Closed-Loop Control. IEICE Transactions 93-C(3): 303-308 (2010) | |
| 76 | Masahiro Hiyama, Makoto Ikeda, Leonard Barolli, Makoto Takizawa: Performance analysis of multi-hop ad-hoc network using multi-flow traffic for indoor scenarios. J. Ambient Intelligence and Humanized Computing 1(4): 283-293 (2010) | |
| 75 | Tao Yang, Makoto Ikeda, Leonard Barolli, Fatos Xhafa, Arjan Durresi: Performance Evaluation of Wireless Sensor Networks for Mobile Event and Mobile Sink. J. Mobile Multimedia 6(4): 281-292 (2010) | |
| 74 | Elis Kulla, Masahiro Hiyama, Makoto Ikeda, Leonard Barolli, Vladi Kolici, Rozeta Miho: MANET performance for source and destination moving scenarios considering OLSR and AODV protocols. Mobile Information Systems 6(4): 325-339 (2010) | |
| 2009 | ||
| 73 | MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. ACM Great Lakes Symposium on VLSI 2009: 177-180 | |
| 72 | Leonard Barolli, Makoto Ikeda, Giuseppe De Marco, Arjan Durresi, Fatos Xhafa: Performance Analysis of OLSR and BATMAN Protocols Considering Link Quality Parameter. AINA 2009: 307-314 | |
| 71 | Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada: Circuit design using stripe-shaped PMELA TFTs on glass. ASP-DAC 2009: 105-106 | |
| 70 | Tao Yang, Leonard Barolli, Makoto Ikeda, Giuseppe De Marco, Fatos Xhafa, Rozeta Miho: Performance Evaluation of a Wireless Sensor Network Considering Mobile Event. CISIS 2009: 1169-1174 | |
| 69 | Makoto Ikeda, Leonard Barolli, Masahiro Hiyama, Giuseppe De Marco, Tao Yang, Arjan Durresi: Performance Evaluation of Link Quality Extension in Multihop Wireless Mobile Ad-hoc Networks. CISIS 2009: 311-318 | |
| 68 | Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda: Measurement of power supply noise tolerance of self-timed processor. DDECS 2009: 128-131 | |
| 67 | Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. DDECS 2009: 206-209 | |
| 66 | Makoto Ikeda, Leonard Barolli, Masahiro Hiyama, Tao Yang, Giuseppe De Marco, Arjan Durresi: Performance Evaluation of a MANET Tested for Different Topologies. NBiS 2009: 327-334 | |
| 65 | Tao Yang, Leonard Barolli, Makoto Ikeda, Fatos Xhafa, Arjan Durresi: Performance Analysis of OLSR Protocol for Wireless Sensor Networks and Comparison Evaluation with AODV Protocol. NBiS 2009: 335-342 | |
| 64 | Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. IEICE Transactions 92-C(6): 798-805 (2009) | |
| 63 | Makoto Ikeda, Leonard Barolli, Giuseppe De Marco, Tao Yang, Arjan Durresi, Fatos Xhafa: Tools for performance assessment of OLSR protocol. Mobile Information Systems 5(2): 165-176 (2009) | |
| 62 | Tao Yang, Leonard Barolli, Makoto Ikeda, Giuseppe De Marco, Arjan Durresi: Performance Evaluation of a Wireless Sensor Network for Mobile and Stationary Event Cases Considering Routing Efficiency and Goodput Metrics. Scalable Computing: Practice and Experience 10(1): (2009) | |
| 2008 | ||
| 61 | Makoto Ikeda, Giuseppe De Marco, Leonard Barolli, Makoto Takizawa: A BAT in the Lab: Experimental Results of New Link State Routing Protocol. AINA 2008: 295-302 | |
| 60 | Tao Yang, Makoto Ikeda, Giuseppe De Marco, Leonard Barolli, Arjan Durresi, Fatos Xhafa: Routing Efficiency of AODV and DSR Protocols in Ad-Hoc Sensor Networks. ICDCS Workshops 2008: 66-71 | |
| 59 | Leonard Barolli, Tao Yang, Makoto Ikeda, Arjan Durresi, Fatos Xhafa: A Simulation System for Routing Efficiency in Wireless Sensor-Actor Networks: A Case Study for Semi-automated Architecture. ICPADS 2008: 567-574 | |
| 58 | Makoto Ikeda, Leonard Barolli, Giuseppe De Marco, Tao Yang, Arjan Durresi: Experimental and Simulation Evaluation of OLSR Protocol for Mobile Ad-Hoc Networks. NBiS 2008: 111-121 | |
| 57 | Leonard Barolli, Makoto Ikeda, Arjan Durresi, Fatos Xhafa, Akio Koyama: Performance Evaluation of Two Search Space Reduction Methods for a Distributed Network Architecture. NBiS 2008: 49-59 | |
| 56 | Makoto Ikeda, Giuseppe De Marco, Tao Yang, Leonard Barolli: Performance analysis of an ad hoc network for emergency and collaborative environments. Telecommunication Systems 38(3-4): 133-146 (2008) | |
| 2007 | ||
| 55 | Giuseppe De Marco, Makoto Ikeda, Tao Yang, Leonard Barolli: Experimental Performance Evaluation of a Pro-Active Ad-hoc Routing Protocol in Out- and Indoor Scenarios. AINA 2007: 7-14 | |
| 54 | Taisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada: Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. ASP-DAC 2007: 100-101 | |
| 53 | Leonard Barolli, Makoto Ikeda, Arjan Durresi, Fatos Xhafa, Akio Koyama: A Distributed QoS Routing and CAC Framework: Performance Evaluation of Its SSRA and InterD Agents. CISIS 2007: 60-67 | |
| 52 | Zhicheng Liang, Makoto Ikeda, Kunihiro Asada: Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology. DDECS 2007: 81-86 | |
| 51 | Tao Yang, Leonard Barolli, Makoto Ikeda, Arjan Durresi, Fatos Xhafa: Network energy consumption in ad-hoc networks under different radio models. ICPADS 2007: 1-8 | |
| 50 | Tao Yang, Makoto Ikeda, Giuseppe De Marco, Leonard Barolli: Performance Behavior of AODV, DSR and DSDV Protocols for Different Radio Models in Ad-Hoc Sensor Networks. ICPP Workshops 2007: 6 | |
| 49 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ISQED 2007: 776-781 | |
| 48 | Makoto Ikeda, Giuseppe De Marco, Leonard Barolli: A Simple Statistical Methodology for Testing Ad Hoc Networks. NBiS 2007: 1-10 | |
| 47 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. IEEE Trans. VLSI Syst. 15(6): 716-720 (2007) | |
| 46 | Leonard Barolli, Makoto Ikeda, Giuseppe De Marco, Arjan Durresi, Akio Koyama, Jiro Iwashige: A Search Space Reduction Algorithm for Improving the Performance of a GA-based QoS Routing Method in Ad-Hoc Networks. IJDSN 3(1): 41-57 (2007) | |
| 45 | Tao Yang, Leonard Barolli, Makoto Ikeda, Arjan Durresi, Fatos Xhafa: Performance Evaluation of Reactive and Proactive Protocols for Ad-Hoc Sensor Networks Using Different Radio Models. Journal of Interconnection Networks 8(4): 387-405 (2007) | |
| 44 | Giuseppe De Marco, Tao Yang, Makoto Ikeda, Leonard Barolli: Performance evaluation of wireless sensor networks for event-detection with shadowing-induced radio irregularities. Mobile Information Systems 3(3-4): 251-266 (2007) | |
| 2006 | ||
| 43 | Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: On-chip 8GHz non-periodic high-swing noise detector. DATE 2006: 670-671 | |
| 42 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Timing-driven cell layout de-compaction for yield optimization by critical area minimization. DATE 2006: 884-889 | |
| 41 | Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. DDECS 2006: 147-148 | |
| 40 | Makoto Ikeda, Leonard Barolli, Giuseppe De Marco, Arjan Durresi, Akio Koyama, Mimoza Durresi: Evaluation of a Network Extraction Topology Algorithm for Reducing Search Space of a GA-based Routing Approach. ICDCS Workshops 2006: 54 | |
| 39 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. ISCAS 2006 | |
| 38 | Tao Yang, Giuseppe De Marco, Makoto Ikeda, Leonard Barolli: A Case Study of Event Detection in Lattice Wireless Sensor Network with Shadowing-Induced Radio Irregularities. MoMM 2006: 241-250 | |
| 37 | Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada: A Structural Approach for Transistor Circuit Synthesis. IEICE Transactions 89-A(12): 3529-3537 (2006) | |
| 36 | Taisuke Kazama, Makoto Ikeda, Kunihiro Asada: LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil. IEICE Transactions 89-A(12): 3546-3550 (2006) | |
| 35 | Toru Nakura, Makoto Ikeda, Kunihiro Asada: Autonomous di/dt Control of Power Supply for Margin Aware Operation. IEICE Transactions 89-C(11): 1689-1694 (2006) | |
| 34 | Toru Nakura, Makoto Ikeda, Kunihiro Asada: Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply. IEICE Transactions 89-C(3): 364-369 (2006) | |
| 33 | Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function. IEICE Transactions 89-C(3): 370-376 (2006) | |
| 32 | Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: Noise Immunity Investigation of Low Power Design Schemes. IEICE Transactions 89-C(8): 1238-1247 (2006) | |
| 31 | Makoto Ikeda, Leonard Barolli, Akio Koyama, Arjan Durresi, Giuseppe De Marco, Jiro Iwashige: Performance evaluation of an intelligent CAC and routing framework for multimedia applications in broadband networks. J. Comput. Syst. Sci. 72(7): 1183-1200 (2006) | |
| 30 | Tao Yang, Giuseppe De Marco, Makoto Ikeda, Leonard Barolli: Impact of radio randomness on performances of lattice wireless sensors networks based on event-reliability concept. Mobile Information Systems 2(4): 211-227 (2006) | |
| 2005 | ||
| 29 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact minimum-width transistor placement without dual constraint for CMOS cells. ACM Great Lakes Symposium on VLSI 2005: 74-77 | |
| 28 | Yusuke Yachide, Yusuke Oike, Makoto Ikeda, Kunihiro Asada: Real-time 3-D measurement system based on light-section method using smart image sensor. ICIP (3) 2005: 1008-1111 | |
| 27 | Makoto Ikeda, Leonard Barolli, Shohei Ohba, Genci Capi, Akio Koyama, Mimoza Durresi: A CAC and Routing Framework for Multimedia Applications in Broadband Networks Using Fuzzy Logic and Genetic Algorithm. ICPADS (1) 2005: 648-654 | |
| 26 | Shohei Ohba, Makoto Ikeda, Leonard Barolli, Giuseppe De Marco, Jiro Iwashige, Arjan Durresi: An Effective Topology Extraction Algorithm for Search Reduction Space of a GA-based QoS Routing Method in Ad-Hoc Networks. ISPAN 2005: 400-405 | |
| 25 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. IEICE Transactions 88-A(12): 3485-3491 (2005) | |
| 24 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Transactions 88-A(7): 1957-1963 (2005) | |
| 23 | Toru Nakura, Makoto Ikeda, Kunihiro Asada: Stub vs. Capacitor for Power Supply Noise Reduction. IEICE Transactions 88-C(1): 125-132 (2005) | |
| 22 | Toru Nakura, Makoto Ikeda, Kunihiro Asada: On-chip di/dt Detector Circuit. IEICE Transactions 88-C(5): 782-787 (2005) | |
| 21 | Toru Nakura, Makoto Ikeda, Kunihiro Asada: Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. IEICE Transactions 88-C(8): 1734-1739 (2005) | |
| 20 | Ulkuhan Ekinciel, Hiroaki Yamaoka, Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada: A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells. IEICE Transactions 88-D(6): 1159-1167 (2005) | |
| 2004 | ||
| 19 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ASP-DAC 2004: 149-154 | |
| 18 | Yusuke Oike, Makoto Ikeda, Kunihiro Asada: Design of real-time VGA 3-D image sensor using mixed-signal techniques. ASP-DAC 2004: 523-524 | |
| 17 | Mohamed Abbas, Makoto Ikeda, Kunihiro Asada: Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime. DFT 2004: 87-95 | |
| 16 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. ISQED 2004: 377-380 | |
| 2003 | ||
| 15 | Yusuke Oike, Makoto Ikeda, Kunihiro Asada: High-speed position detector using new row-parallel architecture for fast collision prevention system. ISCAS (4) 2003: 788-791 | |
| 14 | Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada: Comparative Study On Verilog-Based And C-Based Hardware Design Education. MSE 2003: 41-42 | |
| 2002 | ||
| 13 | Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada: Logic synthesis for PLA with 2-input logic elements. ISCAS (3) 2002: 373-376 | |
| 12 | Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada: Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. VLSI Design 2002: 166-171 | |
| 2001 | ||
| 11 | Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada: A smart position sensor for 3-D measurement. ASP-DAC 2001: 21-22 | |
| 10 | Jian Qiao, Makoto Ikeda, Kunihiro Asada: Finding an optimal functional decomposition for LUT-based FPGA synthesis. ASP-DAC 2001: 225-230 | |
| 9 | Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada: A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. ASP-DAC 2001: 3-4 | |
| 8 | Yusuke Nakashima, Makoto Ikeda, Kunihiro Asada: Computational Cost Reduction in Extracting Inductance. ISQED 2001: 179-184 | |
| 2000 | ||
| 7 | Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada: A binary image sensor with flexible motion vector detection using block matching method. ASP-DAC 2000: 21-22 | |
| 6 | Jian Qiao, Makoto Ikeda, Kunihiro Asada: Optimum Functional Decomposition for LUT-Based FPGA Synthesis. FPL 2000: 555-564 | |
| 5 | Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada: DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path. ISQED 2000: 305-308 | |
| 1999 | ||
| 4 | Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada: Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. Great Lakes Symposium on VLSI 1999: 368-371 | |
| 3 | Makoto Ikeda, Kunihiro Asada: Standard design flows of Logic LSIs in Japanese universities and VDEC. MSE 1999: 8-9 | |
| 1998 | ||
| 2 | Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada: Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. ASP-DAC 1998: 323-324 | |
| 1994 | ||
| 1 | Makoto Ikeda, Kunihiro Asada: A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. EDAC-ETC-EUROASIC 1994: 546-550 | |
Colors in the list of coauthors
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