Tetsuya Iizuka

	2012
19		Tetsuya Iizuka, Kunihiro Asada: All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Transactions 95-C(4): 627-634 (2012)
18		Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada: A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Transactions 95-C(4): 661-667 (2012)
	2011
17		Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC 2011: 79-80
16		Tetsuya Iizuka, Kunihiro Asada: An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. DDECS 2011: 115-120
15		Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada: A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC 2011: 399-402
14		Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada: All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Transactions 94-C(4): 487-494 (2011)
13		Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Transactions 94-C(4): 654-662 (2011)
12		Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada: 1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Transactions 94-C(6): 1098-1104 (2011)
	2010
11		Tetsuya Iizuka, Toru Nakura, Kunihiro Asada: Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS 2010: 167-172
	2007
10		Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ISQED 2007: 776-781
9		Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. IEEE Trans. VLSI Syst. 15(6): 716-720 (2007)
	2006
8		Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Timing-driven cell layout de-compaction for yield optimization by critical area minimization. DATE 2006: 884-889
7		Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. ISCAS 2006
	2005
6		Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact minimum-width transistor placement without dual constraint for CMOS cells. ACM Great Lakes Symposium on VLSI 2005: 74-77
5		Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. IEICE Transactions 88-A(12): 3485-3491 (2005)
4		Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Transactions 88-A(7): 1957-1963 (2005)
	2004
3		Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ASP-DAC 2004: 149-154
2		Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada: Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. ISQED 2004: 377-380
	1998
1		Yuichi Iizuka, Hisako Shiohara, Tetsuya Iizuka, Seiji Isobe: Automatic Visualization Method for Visual Data Mining. PAKDD 1998: 173-185

Coauthor Index

1	Kunihiro Asada	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
2	Yutaka Chiba	[18]
3	Yuichi Iizuka	[1]
4	Makoto Ikeda	[2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [14] [17]
5	Seiji Isobe	[1]
6	Jaehyun Jeong	[14] [17]
7	Kazutoshi Kodama	[15]
8	Shunichi Kubo	[18]
9	Shingo Mandai	[12] [13]
10	Satoshi Miura	[18]
11	Toru Nakura	[11] [12] [13] [14] [17]
12	Hisako Shiohara	[1]
13	Ryota Yamamoto	[18]

Colors in the list of coauthors

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