Masahiro Iida

	2012
24		Masahiro Iida, Motoki Amagasaki, Yasuhiro Okamoto, Qian Zhao, Toshinori Sueyoshi: COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. IEICE Transactions 95-D(2): 294-302 (2012)
23		Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi: An Easily Testable Routing Architecture and Prototype Chip. IEICE Transactions 95-D(2): 303-313 (2012)
	2011
22		Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: An Easily Testable Routing Architecture and Efficient Test Technique. FPL 2011: 291-294
21		Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi: An easily testable routing architecture of FPGA. VLSI-SoC 2011: 106-109
20		Qian Zhao, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. Embedded Systems Letters 3(3): 89-92 (2011)
19		Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi: A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Transactions 94-C(4): 548-556 (2011)
18		Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: Parallelization of the channel width search for FPGA routing. SIGARCH Computer Architecture News 39(4): 82-85 (2011)
	2010
17		Yoshihiro Ichinomiya, Shiro Tanoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. FCCM 2010: 47-54
16		Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi: First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. FPL 2010: 298-303
15		Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. FPL 2010: 304-309
14		Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A robust reconfigurable logic device based on less configuration memory logic cell. FPT 2010: 162-169
13		Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi: Power-aware FPGA routing fabrics and design tools. VLSI-SoC 2010: 67-72
12		Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. TRETS 4(1): 5 (2010)
	2009
11		Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi: A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC 2009: 97-109
10		Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi: Improvement of Execution Efficiency on the MX Core. PDCAT 2009: 420-425
	2008
9		Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, Toshinori Sueyoshi: An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture. Int. J. Reconfig. Comp. 2008: (2008)
	2007
8		Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi: Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. ARC 2007: 142-154
7		Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi: A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM 2007: 285-286
6		Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi: A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. FCCM 2007: 309-310
5		Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi: A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. FPL 2007: 550-553
4		Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi: A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices. IEICE Transactions 90-D(12): 1986-1989 (2007)
	2006
3		Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi: Effective clustering technique to optimize routability of outer cluster nets. FPGA 2006: 229
2		Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi: Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. VLSI-SoC 2006: 198-203
	2005
1		Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi: Applying the Small-World Network to Routing Structure of FPGAs. FPL 2005: 65-70

Coauthor Index

1	Motoki Amagasaki	[2] [5] [8] [9] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24]
2	Jyunya Eto	[13]
3	Naoto Hamabe	[2]
4	Yoshinobu Ichida	[16] [19] [23]
5	Yoshihiro Ichinomiya	[14] [15] [17] [20]
6	Jun Iida	[16] [19] [23]
7	Kazuki Inoue	[11] [12] [19] [21] [22] [23]
8	Masaki Kobata	[3]
9	Masahiro Koga	[9] [16] [19] [23]
10	Morihiro Kuga	[13] [17] [18]
11	Kazunori Matsuyama	[2] [5] [8]
12	Hideaki Monji	[4] [6] [7]
13	Mitsutaka Nakano	[10]
14	Hideaki Nakayama	[2] [8]
15	Shoichi Nishida	[13]
16	Yasuhiro Okamoto	[12] [14] [15] [24]
17	Mitsuro Saji	[16] [19] [23]
18	Hiroomi Sawada	[18]
19	Takurou Shimokawa	[2]
20	Hiroshi Shinohara	[4] [6] [7]
21	Toshinori Sueyoshi	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24]
22	Shiro Tanoue	[17]
23	Hisashi Tsukiashi	[1]
24	Ryoichi Yamaguchi	[2] [5] [8] [9]
25	Hiroki Yosho	[12] [22]
26	Qian Zhao	[12] [14] [20] [24]

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