Paolo Ienne

	2012
108		Xavier Jimenez, David Novo, Paolo Ienne: Software controlled cell bit-density to improve NAND flash lifetime. DAC 2012: 229-234
107		Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne: Selective flexibility: Breaking the rigidity of datapath merging. DATE 2012: 1543-1548
106		Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne: Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. FPGA 2012: 119-128
105		Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk: Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264
104		Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, Wayne Burleson: An architecture-independent instruction shuffler to protect against side-channel attacks. TACO 8(4): 20 (2012)
103		Madhura Purnaprajna, Paolo Ienne: Making wide-issue VLIW processors viable on FPGAs. TACO 8(4): 33 (2012)
	2011
102		Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca: 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011 IEEE 2011
101		Elisardo Antelo, David Hough, Paolo Ienne: 20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011 IEEE Computer Society 2011
100		Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici: Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. DAC 2011: 1014-1019
99		Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne: A first step towards automatic application of power analysis countermeasures. DAC 2011: 230-235
98		Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne: Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA 2011: 237-246
97		Hadi Parandeh-Afshar, Paolo Ienne: Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. FPL 2011: 225-231
96		Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne: Compressor tree synthesis on commercial high-performance FPGAs. TRETS 4(4): 39 (2011)
	2010
95		Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul: A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC 2010: 707-712
94		Hadi Parandeh-Afshar, Paolo Ienne: Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. FCCM 2010: 229-236
93		Amit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL 2010: 19-24
92		Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne: Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. HiPEAC 2010: 126-140
91		Xiaochun Ye, Dongrui Fan, Wei Lin, Nan Yuan, Paolo Ienne: High performance comparison-based sorting algorithm on many-core GPUs. IPDPS 2010: 1-10
90		Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Paolo Ienne: Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. VLSI Syst. 18(4): 578-590 (2010)
89		Ajay K. Verma, Philip Brisk, Paolo Ienne: Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 341-354 (2010)
88		Philip Brisk, Ajay K. Verma, Paolo Ienne: An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1096-1109 (2010)
	2009
87		Amit Verma, Ajay K. Verma, Philip Brisk, Paolo Ienne: Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC 2009: 203-209
86		Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne: A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219
85		Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon: Way Stealing: cache-assisted automatic instruction set extensions. DAC 2009: 31-36
84		Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne: FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM 2009: 267-270
83		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj: 3D configuration caching for 2D FPGAs. FPGA 2009: 286
82		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL 2009: 242-249
81		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510
80		Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne: MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC 2009: 183-197
79		Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD 2009: 689-696
78		Ajay K. Verma, Philip Brisk, Paolo Ienne: Iterative layering: Optimizing arithmetic circuits by structuring the information flow. ICCAD 2009: 797-804
77		Ajay K. Verma, Philip Brisk, Paolo Ienne: Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic 2009: 213-218
76		Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne: Introducing control-flow inclusion to support pipelining in custom instruction set extensions. SASP 2009: 114-121
75		Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne: Arithmetic optimization for custom instruction set synthesis. SASP 2009: 54-57
74		Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne: Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. SiPS 2009: 115-120
73		Philip Brisk, Ajay K. Verma, Paolo Ienne: Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Design Autom. for Emb. Sys. 13(1-2): 115-137 (2009)
72		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne: Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. TRETS 2(2): (2009)
71		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. TRETS 2(3): (2009)
70		Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Transactions on Computational Science 4: 230-243 (2009)
	2008
69		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143
68		Ajay K. Verma, Philip Brisk, Paolo Ienne: Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC 2008: 334-339
67		Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Design space exploration for field programmable compressor trees. CASES 2008: 207-216
66		Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon: Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS 2008: 243-248
65		Ajay K. Verma, Philip Brisk, Paolo Ienne: Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE 2008: 1250-1255
64		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261
63		Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, Israel Koren: Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?. DFT 2008: 202-210
62		Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne: A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180
61		Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne: Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190
60		Maurizio Skerlj, Paolo Ienne: Error Protected Data Bus Inversion Using Standard DRAM Components. ISQED 2008: 35-42
59		Paolo Ienne, P. Petrov: Guest Editorial Special Section on Application Specific Processors. IEEE Trans. VLSI Syst. 16(10): 1257-1258 (2008)
58		Ajay K. Verma, Philip Brisk, Paolo Ienne: Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1761-1774 (2008)
	2007
57		Ajay K. Verma, Paolo Ienne: Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. ASP-DAC 2007: 601-608
56		Ajay K. Verma, Philip Brisk, Paolo Ienne: Rethinking custom ISE identification: a new processor-agnostic method. CASES 2007: 125-134
55		Philip Brisk, Ajay K. Verma, Paolo Ienne: An optimistic and conservative register assignment heuristic for chordal graphs. CASES 2007: 209-217
54		Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar: Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337
53		Ajay K. Verma, Philip Brisk, Paolo Ienne: Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC 2007: 404-409
52		Ajay K. Verma, Paolo Ienne: Automatic synthesis of compressor trees: reevaluating large counters. DATE 2007: 443-448
51		Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar: Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. DFT 2007: 508-516
50		Philip Brisk, Ajay K. Verma, Paolo Ienne: Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD 2007: 172-179
49		Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS 2007: 209-214
48		Frederic Worm, Patrick Thiran, Paolo Ienne: Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs. ISQED 2007: 861-866
47		Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement CoRR abs/0710.4820: (2007)
46		Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: Introduction of Architecturally Visible Storage in Instruction Set Extensions. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 435-446 (2007)
	2006
45		Ajay K. Verma, Paolo Ienne: Towards the automatic exploration of arithmetic-circuit architectures. DAC 2006: 445-450
44		Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi: Automatic identification of application-specific functional units with architecturally visible storage. DATE 2006: 212-217
43		Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma: Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. DATE 2006: 218-223
42		Frederic Worm, Patrick Thiran, Paolo Ienne: Designing Robust Checkers in the Presence of Massive Timing Errors. IOLTS 2006: 281-286
41		Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi: Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design 2006: 651-656
40		Derin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici: A Predictable Communication Scheme for Embedded Multiprocessor Systems. VLSI-SoC 2006: 152-157
39		Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. VLSI Syst. 14(7): 754-762 (2006)
38		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Virtual memory window for application-specific reconfigurable coprocessors. IEEE Trans. VLSI Syst. 14(8): 910-915 (2006)
37		Laura Pozzi, Kubilay Atasu, Paolo Ienne: Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1209-1229 (2006)
	2005
36		Frederic Worm, Patrick Thiran, Paolo Ienne: A Unified Coding Framework for Delay-Insensitivity. ASYNC 2005: 201-211
35		Laura Pozzi, Paolo Ienne: Exploiting pipelining to relax register-file port constraints of instruction-set extensions. CASES 2005: 2-10
34		Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne: Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. CODES+ISSS 2005: 243-248
33		Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE 2005: 1246-1251
32		Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici: Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTImedia 2005: 135-140
31		Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne: Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. ISCAS (2) 2005: 1782-1785
30		Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli: Self-calibrating networks-on-chip. ISCAS (3) 2005: 2361-2364
29		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Seamless Hardware-Software Integration in Reconfigurable Computing Systems. IEEE Design & Test of Computers 22(2): 102-113 (2005)
28		Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli: A robust self-calibrating transmission scheme for on-chip networks. IEEE Trans. VLSI Syst. 13(1): 126-139 (2005)
	2004
27		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. ASAP 2004: 339-351
26		Marc Epalza, Paolo Ienne, Daniel Mlynek: Dynamic Reallocation of Functional Units in Superscalar Processors. Asia-Pacific Computer Systems Architecture Conference 2004: 185-198
25		Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt: Introduction of local memory elements in instruction set extensions. DAC 2004: 729-734
24		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Virtual memory window for application-specific reconfigurable coprocessors. DAC 2004: 948-953
23		Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne: Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. DATE 2004: 748
22		Paolo Ienne, Ajay K. Verma: Arithmetic Transformations to Maximise the Use of Compressor Trees. DELTA 2004: 219-224
21		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. FCCM 2004: 24-33
20		Miljan Vuletic, Laura Pozzi, Paolo Ienne: Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. FPL 2004: 596-605
19		Frederic Worm, Paolo Ienne, Patrick Thiran: Soft self-synchronising codes for self-calibrating communication. ICCAD 2004: 440-447
18		Ajay K. Verma, Paolo Ienne: Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. ICCAD 2004: 791-798
17		Marc Epalza, Paolo Ienne, Daniel Mlynek: Adding Limited Reconfigurability to Superscalar Processors. IEEE PACT 2004: 53-62
16		Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne: Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. SCOPES 2004: 17-32
15		Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli: On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations. IEEE Design & Test of Computers 21(6): 524-535 (2004)
	2003
14		Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli: Automatic Instruction Set Extension and Utilization for Embedded Processors. ASAP 2003: 108-
13		Kubilay Atasu, Laura Pozzi, Paolo Ienne: Automatic application-specific instruction-set extensions under microarchitectural constraints. DAC 2003: 256-261
12		Kubilay Atasu, Laura Pozzi, Paolo Ienne: Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. International Journal of Parallel Programming 31(6): 411-428 (2003)
	2002
11		Laura Pozzi, Miljan Vuletic, Paolo Ienne: Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. DATE 2002: 1138
10		M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha: A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS 2002: 2-7
9		Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm: An Adaptive Low-Power Transmission Scheme for On-Chip Networks. ISSS 2002: 92-100
	1998
8		Paolo Ienne, Alexander Grießing: Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? DAC 1998: 396-401
	1997
7		Paolo Ienne: Digital Connectionist Hardware: Current Problems and Future Challenges. IWANN 1997: 688-713
	1996
6		Thierry Cornu, Paolo Ienne, Dagmar Niebur, Patrick Thiran, Marc A. Viredaz: Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator. Scientific Programming 5(1): 47-61 (1996)
5		Paolo Ienne, Thierry Cornu, Gary Kuhn: Special-purpose digital hardware for neural networks: An architectural survey. VLSI Signal Processing 13(1): 5-25 (1996)
	1995
4		Paolo Ienne: Horizontal Microcode Compaction for Programmable Systolic Accelerators. ASAP 1995: 85-
3		Paolo Ienne, Marc A. Viredaz: GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. VLSI Signal Processing 9(3): 257-273 (1995)
	1994
2		Paolo Ienne, Marc A. Viredaz: Bit-Serial Multipliers and Squarers. IEEE Trans. Computers 43(12): 1445-1450 (1994)
	1993
1		Francesco Mondada, Edoardo Franzi, Paolo Ienne: Mobile Robot Miniaturisation: A Tool for Investigation in Control Algorithms. ISER 1993: 501-513

Coauthor Index

1	Elisardo Antelo	[101]
2	Kubilay Atasu	[12] [13] [25] [37]
3	Panagiotis Athanasopoulos	[61] [72] [79] [81] [83]
4	Stéphane Badel	[49] [86] [100]
5	M. Balakrishnan	[10]
6	Sudarshan Banerjee	[33] [39] [41] [47]
7	Ali Galip Bayrak	[99] [104]
8	Hind Benbihi	[106]
9	Partha Biswas	[25] [33] [39] [41] [44] [46] [47]
10	Jani Boutellier	[74]
11	Luca Breveglieri	[51] [63]
12	Philip Brisk	[50] [53] [54] [55] [56] [58] [61] [62] [64] [65] [66] [67] [68] [69] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81] [82] [83] [84] [85] [86] [87] [88] [89] [90] [92] [93] [95] [96] [98] [99] [105] [107]
13	Wayne P. Burleson (Wayne Burleson)	[104]
14	Samuel Burri	[92]
15	Joseph R. Cavallaro	[102]
16	Alessandro Cevrero	[61] [67] [72] [74] [81] [83] [84] [86] [100]
17	Edoardo Charbon	[66] [80] [85] [92]
18	Vinay Choudhary	[25]
19	Thierry Cornu	[5] [6]
20	Alper Demir	[32]
21	Zeynep Toprak Deniz	[49] [70]
22	Christophe Dubach	[34]
23	Nikil D. Dutt (Nikil Dutt)	[25] [33] [39] [41] [44] [46] [47]
24	Thomas Eisenbarth	[49] [51] [63] [70]
25	Marc Epalza	[17] [26]
26	Milos D. Ercegovac	[102]
27	Nuria Pazos Escudero	[31]
28	Dongrui Fan	[91]
29	Edoardo Franzi	[1]
30	Anup Gangwar	[10]
31	Nithin George	[105]
32	Alexander Grießing	[8]
33	Johann Großschädl	[43] [49] [51] [70]
34	Frank K. Gürkaynak	[61] [67] [70] [72]
35	Frank Hannig	[102]
36	Derin Derin Harmanci	[40]
37	Mehmet Derin Harmanci	[31]
38	David Hough	[101]
39	Diviya Jain	[16]
40	Xavier Jimenez	[108]
41	Theo Kluter	[66] [76] [80] [85] [86] [92]
42	Israel Koren	[51] [63]
43	Gary Kuhn	[5]
44	Anshul Kumar	[10] [16] [95]
45	Yusuf Leblebici	[31] [32] [40] [49] [61] [67] [70] [72] [79] [81] [83] [86] [100]
46	Guy Lemieux (Guy G. Lemieux, Guy G. F. Lemieux)	[105]
47	Wei Lin	[91]
48	Marco Macchetti	[49] [70]
49	Giovanni De Micheli	[9] [14] [15] [28] [30]
50	Bhuvan Middha	[10]
51	Daniel Mlynek	[17] [26]
52	Yehdhih Ould Mohammed Moctar	[105]
53	Francesco Mondada	[1]
54	Arkosnato Neogy	[96]
55	Seyed Hosein Attarzadeh Niaki	[67] [72]
56	Chrysostomos Nicopoulos	[67] [72]
57	Dagmar Niebur	[6]
58	David Novo	[106] [107] [108]
59	Christof Paar	[49] [51] [70]
60	Arun Paidimarri	[84]
61	Hadi Parandeh-Afshar	[54] [61] [62] [64] [69] [71] [72] [81] [82] [83] [90] [93] [94] [96] [97] [98] [105] [106]
62	Kolin Paul	[95]
63	Nuria Pazos	[40]
64	P. Petrov	[59]
65	Armita Peymandoust	[14]
66	Axel Poschmann	[49] [70]
67	Nagaraju Pothineni	[95]
68	Laura Pozzi	[11] [12] [13] [14] [16] [20] [21] [23] [24] [25] [27] [29] [33] [34] [35] [37] [38] [39] [41] [43] [44] [46] [47] [49] [70]
69	Madhura Purnaprajna	[103]
70	Francesco Regazzoni	[49] [51] [63] [70] [86] [99] [100]
71	Ludovic Righetti	[23]
72	Lazar Saranovac	[107]
73	Micheal Schwander	[100]
74	Maurizio Skerlj	[60] [81] [83]
75	François-Xavier Standaert	[86] [99]
76	Mirjana Stojilovic	[107]
77	Earl E. Swartzlander Jr.	[102]
78	Serdar Tasiran	[32]
79	Alexandre F. Tenca	[102]
80	Patrick Thiran	[6] [9] [15] [19] [28] [30] [36] [42] [48]
81	Stefan Tillich	[43]
82	Nigel P. Topham	[76]
83	Nikola Velickovic	[104]
84	Ajay K. Verma	[18] [22] [43] [45] [50] [52] [53] [54] [55] [56] [57] [58] [61] [65] [68] [72] [73] [75] [77] [78] [87] [88] [89] [90] [93]
85	Amit Verma	[87] [93]
86	Marc A. Viredaz	[2] [3] [6]
87	Miljan Vuletic	[11] [20] [21] [23] [24] [27] [29] [34] [38]
88	Frederic Worm	[9] [15] [19] [28] [30] [36] [42] [48]
89	Soner Yaldiz	[32]
90	Xiaochun Ye	[91]
91	Nan Yuan	[91]
92	Grace Zgheib	[98]
93	Yi Zhu	[75]
94	Marcela Zuluaga	[76]

Colors in the list of coauthors

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page