Wei Hwang

	2012
50		Wei-Chih Hsieh, Wei Hwang: All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation. IEEE Trans. VLSI Syst. 20(6): 989-1001 (2012)
49		Po-Tsang Huang, Wei Hwang: Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. J. Electrical and Computer Engineering 2012: (2012)
48		Ming-Hung Chang, Shang-Yuan Lin, Wei Hwang: A 0.4 V 520 nW 990 μm2 Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS. J. Low Power Electronics 8(1): 63-72 (2012)
	2011
47		Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang: Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation. ISLPED 2011: 15-20
46		Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang: A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. ISLPED 2011: 291-296
45		Po-Tsang Huang, Yung Chang, Wei Hwang: On-demand memory sub-system for multi-core SoCs. SoCC 2011: 122-127
44		Wei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, Wei Hwang: An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. SoCC 2011: 19-23
43		Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu: A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC 2011: 197-200
42		Wei-Chih Hsieh, Wei Hwang: Adaptive Power Control Technique on Power-Gated Circuitries. IEEE Trans. VLSI Syst. 19(7): 1167-1180 (2011)
41		Hao-I Yang, Wei Hwang, Ching-Te Chuang: Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. IEEE Trans. VLSI Syst. 19(7): 1192-1204 (2011)
40		Hao-I Yang, Shyh-Chyi Yang, Wei Hwang, Ching-Te Chuang: Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. IEEE Trans. on Circuits and Systems 58-I(6): 1239-1251 (2011)
39		Po-Tsang Huang, Wei Hwang: Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. IEICE Transactions 94-A(11): 2412-2424 (2011)
38		Po-Tsang Huang, Wei Hwang: A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. J. Solid-State Circuits 46(2): 507-519 (2011)
37		Hao-I Yang, Wei Hwang, Ching-Te Chuang: Impacts of gate-oxide breakdown on power-gated SRAM. Microelectronics Journal 42(1): 101-112 (2011)
	2010
36		Wei-Chih Hsieh, Wei Hwang: Low quiescent current variable output digital controlled voltage regulator. ISCAS 2010: 609-612
35		Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, Wei Hwang: Fully on-chip temperature, process, and voltage sensors. ISCAS 2010: 897-900
34		Tien-Hung Lin, Po-Tsang Huang, Wei Hwang: Power noise suppression technique using active decoupling capacitor for TSV 3D integration. SoCC 2010: 209-212
33		Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang: A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electronics 6(4): 551-562 (2010)
	2009
32		Hao-I Yang, Ching-Te Chuang, Wei Hwang: Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. ISCAS 2009: 377-380
31		Yi-Ming Chang, Ming-Hung Chang, Wei Hwang: A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm. SoCC 2009: 115-118
30		Po-Tsang Huang, Wei Hwang: An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. SoCC 2009: 375-378
	2008
29		Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang: "Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS 2008: 3322-3325
28		Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang: A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS 2008: 3342-3345
27		Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang: Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS 2008: 77-83
26		Mu-Tien Chang, Po-Tsang Huang, Wei Hwang: A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC 2008: 175-178
25		Wei-Chih Hsieh, Wei Hwang: In-situ self-aware adaptive power control system with multi-mode power gating network. SoCC 2008: 215-218
24		Hao-I Yang, Ssu-Yun Lai, Wei Hwang: Low-power floating bitline 8-T SRAM design with write assistant circuits. SoCC 2008: 239-242
23		Ming-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang: A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. SoCC 2008: 97-100
	2007
22		Ming-Hung Chang, Zong-Xi Yang, Wei Hwang: A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. ISCAS 2007: 1137-1140
21		Wei-Chih Hsieh, Wei Hwang: Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. ISCAS 2007: 1637-1640
20		Mu-Tien Chang, Po-Tsang Huang, Wei Hwang: A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC 2007: 207-210
19		Chang-Hsuan Chang, Ming-Hung Chang, Wei Hwang: A flexible two-layer external memory management for H.264/AVC decoder. SoCC 2007: 219-222
	2006
18		Po-Tsang Huang, Wei-Keng Chang, Wei Hwang: Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS 2006: 1301-1304
17		Chi-Chen Lai, Wei Hwang: A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor. APCCAS 2006: 1931-1934
16		Jen-Wei Yang, Po-Tsang Huang, Wei Hwang: On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS 2006: 666-669
15		Po-Tsang Huang, Wei Hwang: 2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS 2006
14		Tzu-Chiang Chao, Wei Hwang: A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. ISCAS 2006
13		Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang: A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. ISCAS 2006
	2005
12		Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen: Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. ISCAS (1) 2005: 444-447
	2004
11		Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang: Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. VLSI Signal Processing 38(2): 101-113 (2004)
	2003
10		Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban: Low-power circuits and technology for wireless digital systems. IBM Journal of Research and Development 47(2-3): 283-298 (2003)
	2001
9		Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang: SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI 2001: 37-42
8		W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi: Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED 2001: 263-266
7		Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann: Design Of Provably Correct Storage Arrays. VLSI Design 2001: 196-
	2000
6		George Gristede, Wei Hwang: A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. ACM Great Lakes Symposium on VLSI 2000: 101-106
5		Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang: "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206
4		Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang: A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49
	1999
3		Rajiv V. Joshi, Wei Hwang: Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design 1999: 526-531
	1997
2		W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi: Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285
1		Wei Hwang, Rajiv V. Joshi, Walter H. Henkels: A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD 1997: 712-717

Coauthor Index

1	Azeez J. Bhavnagarwala	[10]
2	Chang-Hsuan Chang	[19]
3	Chi-Shin Chang	[43]
4	Hsie-Chia Chang	[33]
5	I-Ming Chang	[23]
6	Ming-Hung Chang	[19] [22] [23] [28] [31] [35] [44] [46] [47] [48]
7	Mu-Tien Chang	[20] [26]
8	Shu-Wei Chang	[29]
9	Wei-Keng Chang	[18]
10	Yi-Ming Chang	[31]
11	Yung Chang	[45]
12	Tzu-Chiang Chao	[14]
13	Chien-Hen Chen	[43]
14	Chih-Kai Chen	[12]
15	Mei-Wei Chen	[47]
16	Shi-Wen Chen	[35]
17	W. Chen	[8]
18	Yin-Nien Chen	[43]
19	Kenneth Chin	[10]
20	Shu-Shin Chin	[11]
21	Yi-Te Chiu	[46]
22	Ching-Te Chuang	[4] [5] [9] [32] [37] [40] [41] [43]
23	Li-Pu Chuang	[23] [28]
24	Wei-Hung Du	[44]
25	B. El-Kareh	[2]
26	Wei-Li Fang	[27]
27	George Gristede	[6] [8] [10]
28	Anne-Marie Haen	[10]
29	Walter H. Henkels	[1]
30	Sangjin Hong	[11]
31	Mao-Chih Hsia	[43]
32	Chung-Ying Hsieh	[47]
33	Wei-Chih Hsieh	[21] [25] [35] [36] [42] [50]
34	Chih-Chiang Hsu	[43]
35	Chung-Hsien Hua	[12] [13]
36	Po-Tsang Huang	[15] [16] [18] [20] [26] [27] [28] [29] [30] [33] [34] [38] [39] [45] [49]
37	Rajiv V. Joshi	[1] [2] [3] [4] [5] [7] [8] [9]
38	Shyh-Jye Jou	[43]
39	Chih-Hao Kan	[28]
40	Yasunao Katayama	[2]
41	Mark B. Ketchen	[10]
42	Suhwan Kim	[10] [11]
43	T. Kirihata	[2]
44	Daniel R. Knebel	[10]
45	Stephen V. Kosonocky	[8] [10]
46	Prabhakar Kudva	[8]
47	Andreas Kuehlmann	[7]
48	Chi-Chen Lai	[17]
49	Shu-Lin Lai	[46]
50	Ssu-Yun Lai	[24]
51	Chen-Yi Lee	[33]
52	Kuen-Di Lee	[43]
53	Wen-Ta Lee	[43]
54	Xin-Ru Lee	[33]
55	Hung-Yu Li	[43]
56	Nan-Chun Lien	[43]
57	Geng-Cing Lin	[43]
58	Shang-Yuan Lin	[48]
59	Tien-Hung Lin	[34]
60	Yi-Wei Lin	[43]
61	Yung-Wei Lin	[43]
62	Wen-Yen Liu	[29]
63	W. K. Luk	[2]
64	Seiji Munetoh	[2]
65	Chi-Wei Peng	[13]
66	Akashi Satoh	[2]
67	Ghavam V. Shahidi	[4]
68	Wei-Chiang Shih	[43]
69	Yin-Ling Wang	[27]
70	Kevin W. Warren	[10]
71	S. C. Wilson	[4] [5]
72	H. Wong	[2]
73	Matthew R. Wordeman	[2]
74	Ya-Ping Wu	[43]
75	P. Xiao	[2]
76	Hao-I Yang	[24] [32] [37] [40] [41] [43]
77	Hao-Yi Yang	[44]
78	Jen-Wei Yang	[16]
79	Shih-Chi Yang	[43]
80	Shyh-Chyi Yang	[40]
81	Zong-Xi Yang	[22]
82	Victor V. Zyuban	[10]

Colors in the list of coauthors

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