TingTing Hwang

	2012
78		Fu-Wei Chen, TingTing Hwang: Clock tree synthesis with methodology of re-use in 3D IC. DAC 2012: 1094-1099
77		Ang-Chih Hsieh, TingTing Hwang: TSV Redundancy: Architecture and Design Issues in 3-D IC. IEEE Trans. VLSI Syst. 20(4): 711-722 (2012)
	2011
76		Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang: Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation. ASP-DAC 2011: 231-236
75		Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang: A physical-location-aware fault redistribution for maximum IR-drop reduction. ASP-DAC 2011: 701-706
74		Hsien-Te Chen, Hong-Long Lin, Zi-Cheng Wang, TingTing Hwang: A new architecture for power network in 3D IC. DATE 2011: 401-406
73		Ang-Chih Hsieh, Yi-Ta Wu, Shau-Yin Tseng, TingTing Hwang: Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms. ICPP 2011: 552-561
	2010
72		Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li: TSV redundancy: Architecture and design issues in 3D IC. DATE 2010: 166-171
71		Shih-Liang Chen, TingTing Hwang, Shu-Ming Chang, Wen-Wei Lin: A Fast Digital Chaotic Generator for Secure Communication. I. J. Bifurcation and Chaos 20(12): 3969-3987 (2010)
70		Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang: Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization. IEEE Trans. VLSI Syst. 18(12): 1686-1695 (2010)
69		Wen-Wen Hsieh, S.-L. Chen, I-Sheng Lin, TingTing Hwang: A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 289-298 (2010)
68		Shih-Liang Chen, TingTing Hwang, Wen-Wei Lin: Randomness Enhancement Using Digitalized Modified Logistic Map. IEEE Trans. on Circuits and Systems 57-II(12): 996-1000 (2010)
	2009
67		Wen-Wen Hsieh, TingTing Hwang: Thermal-aware post compilation for VLIW architectures. ASP-DAC 2009: 606-611
66		Hsien-Te Chen, Chieh-Chun Chang, TingTing Hwang: New spare cell design for IR drop minimization in Engineering Change Order. DAC 2009: 402-407
65		Wen-Wen Hsieh, I-Sheng Lin, TingTing Hwang: A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test. DATE 2009: 1234-1237
64		Ang-Chih Hsieh, TingTing Hwang: Thermal-aware memory mapping in 3D designs. DATE 2009: 1361-1366
63		Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang: Skew-aware polarity assignment in clock tree. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
62		Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma: Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. ACM Trans. Design Autom. Electr. Syst. 14(4): (2009)
	2008
61		Po-Yuan Chen, Che-Yu Liu, TingTing Hwang: Transition-aware decoupling-capacitor allocation in power noise reduction. ICCAD 2008: 426-429
60		Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang: Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
59		Shih-Liang Chen, Shu-Ming Chang, Wen-Wei Lin, TingTing Hwang: Digital Secure-Communication Using Robust Hyper-Chaotic Systems. I. J. Bifurcation and Chaos 18(11): 3325-3339 (2008)
	2007
58		Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang: Skew aware polarity assignment in clock tree. ICCAD 2007: 376-379
57		Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang: A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007)
56		Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang: A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2222-2227 (2007)
55		Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 564-573 (2007)
54		Yi-Yu Liu, TingTing Hwang: Crosstalk-Aware Domino-Logic Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1155-1161 (2007)
53		Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, TingTing Hwang: Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. The Journal of Supercomputing 42(2): 201-223 (2007)
	2006
52		Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang: Switching-activity driven gate sizing and Vth assignment for low power design. ASP-DAC 2006: 576-581
51		Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang: A bus architecture for crosstalk elimination in high performance processor design. CODES+ISSS 2006: 247-252
50		Yi-Yu Liu, TingTing Hwang: Crosstalk-aware domino logic synthesis. DATE 2006: 1312-1317
49		Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-driven crosstalk elimination at post-compiler level. ISCAS 2006
48		Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11(4): 880-889 (2006)
47		Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang: Crosstalk minimization in logic synthesis for PLAs. ACM Trans. Design Autom. Electr. Syst. 11(4): 890-915 (2006)
46		Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. VLSI Syst. 14(1): 81-85 (2006)
45		Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang: Instruction buffering for nested loops in low-power design. IEEE Trans. VLSI Syst. 14(7): 780-784 (2006)
	2005
44		Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu: Low-power techniques for network security processors. ASP-DAC 2005: 355-360
43		Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu: Functionality directed clustering for low power MTCMOS design. ASP-DAC 2005: 862-867
42		Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) 2005: 3311-3314
	2004
41		Yen-Te Ho, TingTing Hwang: Low power design using dual threshold voltage. ASP-DAC 2004: 205-208
40		Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of Instruction Decoder for Low Power Design. DATE 2004: 664-665
39		Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang: Crosstalk Minimization in Logic Synthesis for PLA. DATE 2004: 790-795
38		Chi-Wei Hu, TingTing Hwang: Output-pattern directed decomposition for low power design. ISCAS (5) 2004: 137-140
37		Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, TingTing Hwang: Power-Aware Scheduling for Parallel Security Processors with Analytical Models. LCPC 2004: 470-484
	2003
36		Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE 2003: 11102-11103
35		Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE 2003: 11134-11135
34		MingHung Lee, TingTing Hwang, Shi-Yu Huang: Decomposition of Extended Finite State Machine for Low Power Design. DATE 2003: 11152-11153
33		Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai: Compiler optimization on VLIW instruction scheduling for low power. ACM Trans. Design Autom. Electr. Syst. 8(2): 252-268 (2003)
	2002
32		Chi Ta Wu, TingTing Hwang: Instruction buffering for nested loops in low power design. ISCAS (4) 2002: 81-84
31		Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu: Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002)
	2001
30		LiYi Lin, Yi-Yu Liu, TingTing Hwang: A construction of minimal delay Steiner tree using two-pole delay model. ASP-DAC 2001: 126-132
29		Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu: Binary decision diagram with minimum expected path length. DATE 2001: 708-712
28		Chau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. IEEE Trans. VLSI Syst. 9(2): 383-389 (2001)
	2000
27		Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai: Compiler Optimization on Instruction Scheduling for Low Power. ISSS 2000: 55-61
	1999
26		Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang: A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. ASP-DAC 1999: 77-80
25		Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu: Logic Transformation for Low Power Synthesis. DATE 1999: 158-162
24		How-Rern Lin, TingTing Hwang: On determining sensitization criterion in an iterative gate sizing process. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 231-238 (1999)
	1998
23		Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang: A Re-engineering Approach to Low Power FPGA Design Using SPFD. DAC 1998: 722-725
22		Chau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. ICCAD 1998: 408-411
21		Chau-Shen Chen, TingTing Hwang: Layout Driven Selection and Chaining of Partial Scan Flip-Flops. J. Electronic Testing 13(1): 19-27 (1998)
	1997
20		Chau-Shen Chen, TingTing Hwang, C. L. Liu: Low Power FPGA Design - A Re-engineering Approach. DAC 1997: 656-661
19		Kuo-Hua Wang, TingTing Hwang: Boolean matching for incompletely specified functions. IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 160-168 (1997)
18		Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang: Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 316-320 (1997)
	1996
17		Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang: Layout Driven Selecting and Chaining of Partial Scan. DAC 1996: 262-267
16		Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu: Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. 1(3): 315-340 (1996)
15		Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang: Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1226-1236 (1996)
14		Kuo-Hua Wang, TingTing Hwang, Cheng Chen: Exploiting communication complexity for Boolean matching. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1249-1256 (1996)
	1995
13		How-Rern Lin, TingTing Hwang: Power recduction by gate sizing with path-oriented slack calculation. ASP-DAC 1995
12		Kuo-Hua Wang, TingTing Hwang: Boolean Matching for Incompletely Specified Functions. DAC 1995: 48-53
11		Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995)
	1994
10		How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang: Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429
9		How-Rern Lin, TingTing Hwang: Dynamical identification of critical paths for iterative gate sizing. ICCAD 1994: 481-484
8		Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: State Assignment for Power and Area Minimization. ICCD 1994: 250-254
7		TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang: Logic synthesis for field-programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1280-1287 (1994)
6		Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin: Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 137-149 (1994)
	1993
5		Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127
	1992
4		Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang: ELM-A Fast Addition Algorithm Discovered by a Program. IEEE Trans. Computers 41(9): 1181-1184 (1992)
3		TingTing Hwang, Robert Michael Owens, Mary Jane Irwin: Efficiently computing communication complexity for multilevel logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 545-554 (1992)
	1990
2		TingTing Hwang, Robert Michael Owens, Mary Jane Irwin: Exploiting communication complexity for multilevel logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 1017-1027 (1990)
	1989
1		TingTing Hwang, Robert Michael Owens, Mary Jane Irwin: Multi-Level Logic Synthesis Using Communication Complexity. DAC 1989: 215-220

Coauthor Index

1	Alex C.-Y. Chang	[35]
2	Chieh-Chun Chang	[66] [70]
3	Ming-Tung Chang	[72]
4	Po-Hsien Chang	[60]
5	Shih-Chieh Chang	[15] [60]
6	Shu-Ming Chang	[59] [71]
7	Tsuang-Wei Chang	[43] [57]
8	Chau-Shen Chen	[5] [11] [17] [20] [21] [22] [28]
9	Cheng Chen	[14]
10	Fu-Wei Chen	[75] [78]
11	Hsien-Te Chen	[66] [70] [74]
12	Po-Yuan Chen	[51] [52] [56] [58] [61] [62] [63]
13	S.-L. Chen	[69]
14	Shih-Liang Chen	[59] [68] [71] [75]
15	Wen-Hsin Chen	[26]
16	Feng-Yi Chiang	[23]
17	Yi-Ling Chiang	[49] [55]
18	Ching-Lung Chou	[10]
19	Sue-Hong Chow	[16]
20	Chiao-Chen Fang	[62]
21	Kuan-Hsien Ho	[58] [63]
22	Yen-Te Ho	[41]
23	Yi-Cheng Ho	[16]
24	Ang-Chih Hsieh	[45] [57] [64] [72] [73] [76] [77]
25	Wen-Wen Hsieh	[51] [56] [65] [67] [69]
26	Sheng-Yu Hsu	[43] [44]
27	Yu-Chin Hsu	[10]
28	Chi-Wei Hu	[38]
29	Chung-Wen Huang	[37] [53]
30	Po-Chiun Huang	[44]
31	Shi-Yu Huang	[34]
32	Yu-Hui Huang	[44] [52]
33	Jan-Min Hwang	[23]
34	Mary Jane Irwin	[1] [2] [3] [4] [7]
35	Yi-Min Jiang	[6]
36	Sung-Mo Kang	[25] [31]
37	Thomas P. Kelliher	[4]
38	Ki-Wook Kim	[25] [31]
39	Taewhan Kim	[31]
40	Wu-An Kuo	[35] [36] [40] [42] [46] [48] [49] [55]
41	Chingren Lee	[27] [33]
42	Jenq Kuen Lee	[27] [33] [37] [53]
43	MingHung Lee	[34]
44	Tsing-Fa Lee	[6]
45	Hung-Chun Li	[72]
46	Hong-Long Lin	[74]
47	How-Rern Lin	[9] [10] [13] [24]
48	I-Sheng Lin	[65] [69]
49	Kuang-Hui Lin	[17]
50	LiYi Lin	[30]
51	Shiuann-Shiuh Lin	[18] [26]
52	Tzu-Teng Lin	[57]
53	Wen-Wei Lin	[26] [59] [68] [71]
54	Youn-Long Lin	[5] [6] [8] [11]
55	Yuh-Ju Lin	[18]
56	Yung-Chia Lin	[37] [53]
57	Yung-Sheng Lin	[75]
58	C. L. Liu (Chung Laung (Dave) Liu)	[16] [20] [22] [25] [28] [29] [31]
59	Che-Yu Liu	[61]
60	Chun-Cheng Liu	[76]
61	Yi-Yu Liu	[29] [30] [39] [47] [50] [54]
62	Jennifer Y.-L. Lo	[36]
63	Hsi-Pin Ma	[62]
64	Malgorzata Marek-Sadowska	[15]
65	Robert Michael Owens	[1] [2] [3] [4] [7]
66	Wei Kuan Shih	[37] [53]
67	Yu-Shih Su	[60]
68	Min-Hsiu Tsai	[72]
69	Shi-Chun Tsai	[27] [33]
70	Yu-Wen Tsay	[5] [11]
71	Chih-Mou Tseng	[72]
72	Chun-Yen Tseng	[44]
73	Shau-Yin Tseng	[73]
74	Chun-Yao Wang	[56]
75	Kuo-Hua Wang	[7] [8] [12] [14] [19] [29] [39] [47]
76	Wen-Sing Wang	[8]
77	Zi-Cheng Wang	[74]
78	Allen C.-H. Wu	[5] [8] [11] [35] [36] [40] [42] [46] [48] [49] [55]
79	Chi Ta Wu	[32] [45]
80	Yi-Ta Wu	[73]
81	Yi-Ping You	[37] [44] [53]

Colors in the list of coauthors

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