Robert E. Huston

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1998

3 Ed Chang, David Cheung, Robert E. Huston, Jim Seaton, Gary Smith: A scalable architecture for VLSI test. ITC 1998: 500-506

1997

2 Robert E. Huston: Pin Margin Analysis. ITC 1997: 655-662

1983

1 Robert E. Huston: An Analysis of ATE Testing Costs. ITC 1983: 396-411

	1998
3		Ed Chang, David Cheung, Robert E. Huston, Jim Seaton, Gary Smith: A scalable architecture for VLSI test. ITC 1998: 500-506
	1997
2		Robert E. Huston: Pin Margin Analysis. ITC 1997: 655-662
	1983
1		Robert E. Huston: An Analysis of ATE Testing Costs. ITC 1983: 396-411

Coauthor Index

1 Ed Chang [3]

2 David Cheung [3]

3 Jim Seaton [3]

4 Gary Smith [3]

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team —

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