 | 2011 |
| 8 |  | Mohd Azman Abdul Latif,
Noohul Basheer Zain Ali,
Fawnizu Azmadi Hussin:
IDVP (Intra-Die Variation Probe) for System-On-Chip (SoC) Infant Mortality screen.
ISCAS 2011: 2055-2058 |
| 2010 |
| 7 |  | Zahraa Elhassan M. Osman,
Fawnizu Azmadi Hussin,
Noohul Basheer Zain Ali:
Optimization of Processor Architecture for Image Edge Detection Filter.
UKSim 2010: 648-652 |
| 2008 |
| 6 |  | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Alex Orailoglu,
Hideo Fujiwara:
Scheduling Power-Constrained Tests through the SoC Functional Bus.
IEICE Transactions 91-D(3): 736-746 (2008) |
| 5 |  | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Hideo Fujiwara:
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time.
IEICE Transactions 91-D(7): 1999-2007 (2008) |
| 4 |  | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Hideo Fujiwara:
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints.
IEICE Transactions 91-D(7): 2008-2017 (2008) |
| 2007 |
| 3 |  | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Alex Orailoglu,
Hideo Fujiwara:
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.
ASP-DAC 2007: 720-725 |
| 2 |  | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Hideo Fujiwara:
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.
European Test Symposium 2007: 35-42 |
| 2006 |
| 1 |  | Fawnizu Azmadi Hussin,
Tomokazu Yoneda,
Alex Orailoglu,
Hideo Fujiwara:
Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
ICCD 2006 |