![]() | ![]() |
Sorin Alexander Huss
List of publications from the DBLP Bibliography Server - FAQ
| 2012 | ||
|---|---|---|
| 78 | Werner Schindler, Sorin A. Huss: Constructive Side-Channel Analysis and Secure Design - Third International Workshop, COSADE 2012, Darmstadt, Germany, May 3-4, 2012. Proceedings Springer 2012 | |
| 77 | Michael Zohner, Michael Kasper, Marc Stöttinger, Sorin A. Huss: Side channel analysis of the SHA-3 finalists. DATE 2012: 1012-1017 | |
| 76 | André Seffrin, Sorin A. Huss: Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only). FPGA 2012: 267 | |
| 2011 | ||
| 75 | Mehmet A. Orgun, Atilla Elçi, Oleg B. Makarevich, Sorin A. Huss, Josef Pieprzyk, Lyudmila K. Babenko, Alexander G. Chefranov, Rajan Shankaran: Proceedings of the 4th International Conference on Security of Information and Networks, SIN 2011, Sydney, NSW, Australia, November 14-19, 2011 ACM 2011 | |
| 74 | Alexander Biedermann, Marc Stöttinger, Lijing Chen, Sorin A. Huss: Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture. ARC 2011: 385-396 | |
| 73 | André Seffrin, Sorin A. Huss: Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms. DDECS 2011: 457-462 | |
| 72 | Sunil Malipatlolla, Thomas Feller, Abdulhadi Shoufan, Tolga Arul, Sorin A. Huss: A novel architecture for a secure update of cryptographic engines on trusted platform module. FPT 2011: 1-6 | |
| 71 | Sunil Malipatlolla, Thomas Feller, Abdulhadi Shoufan, Tolga Arul, Sorin A. Huss: A novel architecture for a secure update of cryptographic engines on trusted platform module. FPT 2011: 1-6 | |
| 70 | André Seffrin, Sorin A. Huss: Hardware-accelerated execution of Pi-calculus reconfiguration schedules. FPT 2011: 1-8 | |
| 69 | Thomas Feller, Sunil Malipatlolla, David Meister, Sorin A. Huss: TinyTPM: A lightweight module aimed to IP protection and trusted embedded platforms. HOST 2011: 6-11 | |
| 68 | Alexander Biedermann, Thorsten Piper, Lars Patzina, Sven Patzina, Sorin A. Huss, Andy Schürr, Neeraj Suri: Enhancing FPGA Robustness via Generic Monitoring IP Cores. PECCS 2011: 379-386 | |
| 67 | Hagen Stübing, Murat Ceven, Sorin A. Huss: A Diffie-Hellman based privacy protocol for Car-to-X communication. PST 2011: 201-204 | |
| 66 | Thomas Feller, Sunil Malipatlolla, Michael Kasper, Sorin A. Huss: dcTPM: A Generic Architecture for Dynamic Context Management. ReConFig 2011: 211-216 | |
| 65 | Hagen Stübing, Marco Pfalzgraf, Sorin A. Huss: A Decentralized Group Privacy Protocol for Vehicular Networks. SocialCom/PASSAT 2011: 1147-1154 | |
| 64 | H. Gregor Molter, André Seffrin, Sorin A. Huss: State space optimization within the DEVS model of computation for timing efficiency. VLSI-SoC 2011: 422-427 | |
| 63 | Hagen Stübing, Jonas Firl, Sorin A. Huss: A two-stage verification process for Car-to-X mobility data based on path prediction and probabilistic maneuver recognition. VNC 2011: 17-24 | |
| 62 | Attila Jaeger, Hagen Stübing, Sorin A. Huss: WiSec 2011 poster: a modular design for a hardware security module in car-to-x communication. Mobile Computing and Communications Review 15(3): 43-44 (2011) | |
| 2010 | ||
| 61 | Oleg B. Makarevich, Atilla Elçi, Mehmet A. Orgun, Sorin A. Huss, Ludmila K. Babenko, Alexander G. Chefranov, Vijay Varadharajan: Proceedings of the 3rd International Conference on Security of Information and Networks, SIN 2010, Rostov-on-Don, Russian Federation, September 7-11, 2010 ACM 2010 | |
| 60 | Marc Stöttinger, Alexander Biedermann, Sorin Alexander Huss: Virtualization within a Parallel Array of Homogeneous Processing Units. ARC 2010: 17-28 | |
| 59 | Abdulhadi Shoufan, Sorin Alexander Huss: Reconfigurable Computing Education in Computer Science. ARC 2010: 329-336 | |
| 58 | Felix Madlener, Julia Weingart, Sorin A. Huss: Verification of dynamically reconfigurable embedded systems by model transformation rules. CODES+ISSS 2010: 33-40 | |
| 57 | Marc Stöttinger, Sorin A. Huss, Sascha Mühlbach, Andreas Koch: Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme. EUC 2010: 603-608 | |
| 56 | André Seffrin, Alexander Biedermann, Sorin A. Huss: Tiny-Pi: A Novel Formal Method for Specification, Analysis and Verification of Dynamic Partial Reconfiguration Processes. FDL 2010: 86-91 | |
| 55 | André Seffrin, Sunil Malipatlolla, Sorin A. Huss: A novel design flow for tamper-resistant self-healing properties of FPGA devices without configuration readback capability. FPT 2010: 291-294 | |
| 54 | Stefan Nürnberger, Thomas Feller, Sorin A. Huss: Ray - a secure micro kernel architecture. PST 2010: 3-6 | |
| 53 | Hagen Stübing, Abdulhadi Shoufan, Sorin Alexander Huss: A Demonstrator for Beamforming in C2X Communication. VTC Spring 2010: 1-2 | |
| 52 | Hagen Stübing, Abdulhadi Shoufan, Sorin Alexander Huss: Enhancing Security and Privacy in C2X Communication by Radiation Pattern Control. VTC Spring 2010: 1-5 | |
| 51 | Marc Stöttinger, Felix Madlener, Sorin A. Huss: Procedures for Securing ECC Implementations Against Differential Power Analysis Using Reconfigurable Architectures. Dynamically Reconfigurable Systems 2010: 395-415 | |
| 50 | Abdulhadi Shoufan, Thorsten Wink, H. Gregor Molter, Sorin A. Huss, Eike Kohnert: A Novel Cryptoprocessor Architecture for the McEliece Public-Key Cryptosystem. IEEE Trans. Computers 59(11): 1533-1546 (2010) | |
| 49 | Abdulhadi Shoufan, Sorin A. Huss: A Course on Reconfigurable Processors. TOCE 10(2): (2010) | |
| 2009 | ||
| 48 | Abdulhadi Shoufan, Thorsten Wink, H. Gregor Molter, Sorin A. Huss, Falko Strenzke: A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms. ASAP 2009: 98-105 | |
| 47 | Felix Madlener, H. Gregor Molter, Sorin A. Huss: SC-DEVS: An efficient SystemC extension for the DEVS model of computation. DATE 2009: 1518-1523 | |
| 46 | Abdulhadi Shoufan, Sorin Alexander Huss: Understanding physical models in VHDL-AMS. FDL 2009: 1-4 | |
| 45 | H. Gregor Molter, André Seffrin, Sorin Alexander Huss: DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code. FDL 2009: 1-6 | |
| 44 | Adeel Israr, Abdulhadi Shoufan, Sorin A. Huss: An efficient reliability evaluation approach for system-level design of embedded systems. ISQED 2009: 339-344 | |
| 43 | Sorin Alexander Huss: Embedded systems for IT security applications: properties and design considerations. SIN 2009: 138-142 | |
| 42 | Osman Ugus, Dirk Westhoff, Ralf Laue, Abdulhadi Shoufan, Sorin A. Huss: Optimized Implementation of Elliptic Curve Based Additive Homomorphic Encryption for Wireless Sensor Networks CoRR abs/0903.3900: (2009) | |
| 41 | Abdulhadi Shoufan, Sorin A. Huss: High-Performance Rekeying Processor Architecture for Group Key Management. IEEE Trans. Computers 58(10): 1421-1434 (2009) | |
| 2008 | ||
| 40 | Adeel Israr, Sorin A. Huss: Specification and Design Considerations for Reliable Embedded Systems. DATE 2008: 1111-1116 | |
| 39 | Ralf Laue, H. Gregor Molter, Felix Rieder, Sorin A. Huss, Kartik Saxena: A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications. ISVLSI 2008: 87-92 | |
| 38 | Abdulhadi Shoufan, Sorin A. Huss, Oliver Kelm, Sebastian Schipp: A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware Architectures. ReConFig 2008: 301-306 | |
| 37 | Abdulhadi Shoufan, Sorin A. Huss: Schlüsselverwaltung im Sicheren Multicast. Sicherheit 2008: 179-191 | |
| 36 | Ralf Laue, Sorin A. Huss: Parallel Memory Architecture for Elliptic Curve Cryptography over GF(p) Aimed at Efficient FPGA Implementation. Signal Processing Systems 51(1): 39-55 (2008) | |
| 2007 | ||
| 35 | Abdulhadi Shoufan, Ralf Laue, Sorin A. Huss: High-Flexibility Rekeying Processor for Key Management in Secure Multicast. AINA Workshops (1) 2007: 822-829 | |
| 34 | Juergen Weber, Andreas C. Lemke, Andreas Lehmler, Mario Anton, Sorin A. Huss: Mixed-Level Modeling Using Configurable MOS Transistor Models. FDL 2007: 6-11 | |
| 33 | Ralf Laue, Oliver Kelm, Sebastian Schipp, Abdulhadi Shoufan, Sorin A. Huss: Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation. FPL 2007: 480-484 | |
| 32 | Abdulhadi Shoufan, Ralf Laue, Sorin A. Huss: Reliable Performance Evaluation of Rekeying Algorithms in Secure Multicast. WOWMOM 2007: 1-8 | |
| 2006 | ||
| 31 | Sorin A. Huss: Analog circuit synthesis: a search for the Holy Grail? ISCAS 2006 | |
| 30 | Kaiping Zeng, Sorin A. Huss: Architecture refinements by code refactoring of behavioral VHDL-AMS models. ISCAS 2006 | |
| 29 | Kaiping Zeng, Sorin A. Huss: Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques. ISQED 2006: 225-230 | |
| 28 | Andreas Kühn, Felix Madlener, Sorin A. Huss: Resource Management for Dynamic Reconfigurable Hardware Structures. ReCoSoC 2006: 111-116 | |
| 2005 | ||
| 27 | Arshad Jhumka, Stephan Klaus, Sorin A. Huss: A Dependability-Driven System-Level Design Approach for Embedded Systems. DATE 2005: 372-377 | |
| 26 | Stephan Hermanns, Sorin A. Huss: Synchronisierungsprobleme von Schaltwerken in Wave Pipelining Architektur und ihre Auswirkungen auf die Wahl der Schaltungstechnik. GI Jahrestagung (1) 2005: 449 | |
| 25 | Abdulhadi Shoufan, Sorin A. Huss, Murtuza Cutleriwala: A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management. HiPEAC 2005: 169-183 | |
| 24 | Kaiping Zeng, Sorin A. Huss: RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis. ISVLSI 2005: 266-267 | |
| 23 | Michael Jung, Ralf Laue, Sorin A. Huss: A Case Study on Partial Evaluation in Embedded Software Design. SEUS 2005: 16-21 | |
| 22 | W. W. Bachmann, Sorin A. Huss: Efficient algorithms for multilevel power estimation of VLSI circuits. IEEE Trans. VLSI Syst. 13(2): 238-254 (2005) | |
| 2004 | ||
| 21 | P. Hastono, Stephan Klaus, Sorin A. Huss: Real-Time Operating System Services for Realistic SystemC Simulation Models of Embedded Systems. FDL 2004: 380-392 | |
| 20 | Song Yuan, Sorin A. Huss: Audio watermarking algorithm for real-time speech integrity and authentication. MM&Sec 2004: 220-226 | |
| 19 | Andreas Kühn, Sorin A. Huss: Dynamically Reconfigurable Hardware for Object-Oriented Processing. PARELEC 2004: 181-186 | |
| 18 | Michael Jung, Sorin A. Huss: Fast Points-to Analysis for Languages with Structured Types. SCOPES 2004: 107-121 | |
| 17 | Jens Bieger, Sorin A. Huss, Michael Jung, Stephan Klaus, Thomas Steininger: Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach. VLSI Design 2004: 577- | |
| 16 | M. Ernst, B. Henhapl, S. Klupsch, Sorin A. Huss: FPGA based hardware acceleration for elliptic curve public key cryptosystems. Journal of Systems and Software 70(3): 299-313 (2004) | |
| 15 | Jens Bieger, Sorin A. Huss: Konzepte zur Beherrschung der Entwurfskomplexität eingebetteter Systeme. it - Information Technology 46(2): 59-66 (2004) | |
| 2003 | ||
| 14 | Stephan Klaus, Sorin A. Huss: A Novel Specification Model for IP-based Design. DSD 2003: 190-196 | |
| 2002 | ||
| 13 | M. Ernst, Michael Jung, Felix Madlener, Sorin A. Huss, Rainer Blümel: A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n). CHES 2002: 381-399 | |
| 2001 | ||
| 12 | M. Ernst, S. Klupsch, O. Hauck, Sorin A. Huss: Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems. IEEE International Workshop on Rapid System Prototyping 2001: 24-31 | |
| 2000 | ||
| 11 | O. Hauck, A. Katoch, Sorin A. Huss: VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip. ASYNC 2000: 188- | |
| 1999 | ||
| 10 | O. Hauck, M. Garg, Sorin A. Huss: Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT. ASYNC 1999: 219- | |
| 9 | O. Hauck, M. Garg, Sorin A. Huss: Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications. Great Lakes Symposium on VLSI 1999: 38-41 | |
| 8 | Wolfgang Boßung, Sorin A. Huss, Stephan Klaus, Lars Wehmeyer: Functional Specification of Distributed Digital Image Processing Systems by Process Interface Descriptions. PDPTA 1999: 2975-2981 | |
| 7 | Wolfgang Boßung, Sorin Alexander Huss, Stephan Klaus: High-Level Embedded System Specifications Based on Process Activation Conditions. VLSI Signal Processing 21(3): 277-291 (1999) | |
| 1998 | ||
| 6 | R. Rosenberger, Sorin A. Huss: A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks. DATE 1998: 721-728 | |
| 1995 | ||
| 5 | Uwe F. Baake, Sorin A. Huss: Logic Reduction in Timed Asynchronous Circuits. ISCAS 1995: 1223-1226 | |
| 4 | Michael Goedecke, Sorin A. Huss, Kai Morich: Automatic Parallelization of the Visual Data-Flow Language Cantata for Efficient Characterization of Analog Circuit Behavior. VL 1995: 69-76 | |
| 1994 | ||
| 3 | Matthias Deegener, Sorin A. Huss: Software/hardware Co-Design in the MuSE environment. CODES 1994: 195-202 | |
| 2 | Uwe F. Baake, Sorin A. Huss: Scheduling of Signal Transition Graphs under Timing Constraints. ISCAS 1994: 205-208 | |
| 1993 | ||
| 1 | Uwe F. Baake, Sorin A. Huss: Object-oriented representation, analysis, and scheduling of signal transition graphs. ISCAS 1993: 2737-2740 | |
Colors in the list of coauthors
Last update Thu May 31 18:55:10 2012 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page