Chia-Lung Hung

	2011
4		Hui-Ya Li, Chia-Lung Hung, Wen-Jyi Hwang, Yi-Tsan Hung: Efficient pipelined architecture for competitive learning. J. Parallel Distrib. Comput. 71(2): 236-244 (2011)
	2010
3		Hui-Ya Li, Chien-Min Ou, Yi-Tsan Hung, Wen-Jyi Hwang, Chia-Lung Hung: Hardware Implementation of k-Winner-Take-All Neural Network with On-chip Learning. CSE 2010: 340-345
2		Hui-Ya Li, Chia-Lung Hung, Wen-Jyi Hwang: An Efficient Pipelined Architecture for Fast Competitive Learning. ICA3PP (2) 2010: 381-390
	2009
1		Hui-Ya Li, Wen-Jyi Hwang, Chih-Chieh Hsu, Chia-Lung Hung: Efficient K-Means VLSI Architecture for Vector Quantization. SCIA 2009: 440-449

Coauthor Index

1	Chih-Chieh Hsu	[1]
2	Yi-Tsan Hung	[3] [4]
3	Wen-Jyi Hwang	[1] [2] [3] [4]
4	Hui-Ya Li	[1] [2] [3] [4]
5	Chien-Min Ou	[3]

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