 | 2011 |
|---|
| 5 |       | Cheng-Liang Hung,
Kuo-Hsing Cheng,
Yu-Chen Lin,
Bo-Qian Jiang,
Che-hao Fan,
Chi-Yang Chang:
A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation.
ESSCIRC 2011: 447-450 |
| 4 | | Kuo-Hsing Cheng,
Cheng-Liang Hung,
Chih-Hsien Chang:
A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique.
J. Solid-State Circuits 46(5): 1198-1213 (2011) |
| 2010 |
|---|
| 3 | | Yo-Hao Tu,
Hsiang-Hao Chang,
Cheng-Liang Hung,
Kuo-Hsing Cheng:
A 3 GHz DLL-based clock generator with stuck locking protection.
ICECS 2010: 106-109 |
| 2008 |
|---|
| 2 | | Kuo-Hsing Cheng,
Cheng-Liang Hung,
Chih-Hsien Chang,
Yu-lung Lo,
Wei-Bin Yang,
Jiunn-Way Miaw:
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III.
DDECS 2008: 64-67 |
| 2007 |
|---|
| 1 | | Kuo-Hsing Cheng,
Cheng-Liang Hung,
Chia-Wei Su:
A Sub-1V Low-Power High-Speed Static Frequency Divider.
ISCAS 2007: 3848-3851 |
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