Leendert M. Huisman

	2004
17		Leendert M. Huisman, Maroun Kassab, Leah Pastel: Data Mining Integrated Circuit Fails with Fail Commonalities. ITC 2004: 661-668
16		Leendert M. Huisman: Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 91-101 (2004)
	2003
15		Peter Wohl, Leendert M. Huisman: Analysis and Design of Optimal Combinational Compactors. VTS 2003: 101-106
	2001
14		Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski: Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. ITC 2001: 287-296
	1998
13		Daniel R. Knebel, Pia Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika: Diagnosis and characterization of timing-related defects by time-dependent light emission. ITC 1998: 733-739
12		Leendert M. Huisman: Correlations between path delays and the accuracy of performance prediction. ITC 1998: 801-808
	1995
11		Leendert M. Huisman: Yield fluctuations and defect models. J. Electronic Testing 7(3): 241-254 (1995)
	1994
10		Peter C. Maxwell, Robert C. Aitken, Leendert M. Huisman: The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability. ITC 1994: 739-746
9		Leendert M. Huisman, Sandip Kundu: Highly Reliable Symmetric Networks. IEEE Trans. Parallel Distrib. Syst. 5(1): 94-97 (1994)
	1992
8		Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy: A Small Test Generator for Large Designs. ITC 1992: 30-40
	1990
7		Leendert M. Huisman, Raja Daoud: Fault simulation of logic designs on parallel processors with distributed memory. ITC 1990: 690-697
	1988
6		Larry Carter, Leendert M. Huisman, Tom W. Williams: TRIM: testability range by ignoring the memory. IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 38-49 (1988)
5		Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman: SLS-a fast switch-level simulator [for MOS]. IEEE Trans. on CAD of Integrated Circuits and Systems 7(8): 838-849 (1988)
	1986
4		Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman: SLS - a fast switch level simulator for verification and fault coverage analysis. DAC 1986: 164-170
3		Leendert M. Huisman, Larry Carter, Tom W. Williams: TRIM : Testability Range by Ignoring the Memory. ITC 1986: 474-479
	1984
2		Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman: Using a Hardware Simulation Engine for Custom MOS Structured Designs. IBM Journal of Research and Development 28(5): 564-571 (1984)
	1983
1		Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo: Simulating pass transistor circuits using logic simulation machines. DAC 1983: 157-163

Coauthor Index

1	Robert C. Aitken (Rob Aitken)	[10]
2	Thomas Bartenstein	[14]
3	Zeev Barzilai	[1] [2] [4] [5]
4	Daniel K. Beece	[2] [4] [5]
5	Larry Carter	[3] [6]
6	Raja Daoud	[7]
7	Douglas Heaberlin	[14]
8	Vijay S. Iyengar	[4] [5] [8]
9	Jeffrey A. Kash	[13]
10	Maroun Kassab	[17]
11	Daniel R. Knebel	[13]
12	Sandip Kundu	[8] [9]
13	Peter C. Maxwell	[10]
14	Moyra K. McManus	[13]
15	Franco Motika	[13]
16	Indira Nair	[8]
17	Phil Nigh	[13]
18	Leah Pastel	[17]
19	Lakshmi N. Reddy	[8]
20	Rick Rizzolo	[13]
21	Pia Sanda	[13]
22	Gabriel M. Silberman	[1] [2] [4] [5]
23	David Sliwinski	[14]
24	Peilin Song	[13]
25	Donald T. Tang	[1]
26	James C. Tsang	[13]
27	David P. Vallett	[13]
28	Tom W. Williams	[3] [6]
29	Peter Wohl	[15]
30	Lin S. Woo	[1]

Colors in the list of coauthors

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