 | 2012 |
|---|
| 5 |       | Juinn-Dar Huang,
Ya-Shih Huang,
Mi-Yu Hsu,
Han-Yuan Chang:
Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only).
FPGA 2012: 268 |
| 2011 |
|---|
| 4 | | Ya-Shih Huang,
Yang-Hsiang Liu,
Juinn-Dar Huang:
Layer-Aware Design Partitioning for Vertical Interconnect Minimization.
ISVLSI 2011: 144-149 |
| 2009 |
|---|
| 3 | | Yu-Ju Hong,
Ya-Shih Huang,
Juinn-Dar Huang:
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture.
ASP-DAC 2009: 19-24 |
| 2 | | Ya-Shih Huang,
Yu-Ju Hong,
Juinn-Dar Huang:
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture.
IEICE Transactions 92-A(12): 3143-3150 (2009) |
| 2008 |
|---|
| 1 | | Wei-Sheng Huang,
Yu-Ru Hong,
Juinn-Dar Huang,
Ya-Shih Huang:
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing.
ASP-DAC 2008: 16-21 |
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