Shih-Hsu Huang

	2012
50		Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng: Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. ASP-DAC 2012: 245-250
	2011
49		Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang: TSV sharing through multiplexing for TSV count minimization in high-level synthesis. SoCC 2011: 156-159
48		Shih-Hsu Huang, Guan-Yu Jhuo, Wei-Lun Huang: Minimum Inserted Buffers for Clock Period Minimization. J. Inf. Sci. Eng. 27(5): 1513-1526 (2011)
47		Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng: Accurate TSV Number Minimization in High-Level Synthesis. J. Inf. Sci. Eng. 27(5): 1527-1543 (2011)
	2010
46		Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan: Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. ASP-DAC 2010: 480-485
45		Shih-Hsu Huang, Chun-Hua Cheng: Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. J. Inf. Sci. Eng. 26(6): 2249-2266 (2010)
	2009
44		Shih-Hsu Huang, Chun-Hua Cheng: Timing driven power gating in high-level synthesis. ASP-DAC 2009: 173-178
43		Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang: Surge Current Minimization in High-level Synthesis. ISCAS 2009: 1513-1516
42		Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh: Opposite-phase register switching for peak current minimization. ACM Trans. Design Autom. Electr. Syst. 14(1): (2009)
41		Shih-Hsu Huang, Chun-Hua Cheng: Minimum-Period Register Binding. IEEE Trans. on CAD of Integrated Circuits and Systems 28(8): 1265-1269 (2009)
40		Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan: Synthesis of Anti-Aging Gated Clock Designs. J. Inf. Sci. Eng. 25(6): 1651-1670 (2009)
39		Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng: Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. J. Inf. Sci. Eng. 25(6): 1707-1722 (2009)
	2008
38		Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu: Type-matching clock tree for zero skew clock gating. DAC 2008: 714-719
37		Shih-Hsu Huang, Chun-Hua Cheng: An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. IEICE Transactions 91-A(1): 375-382 (2008)
36		Shih-Hsu Huang, Chun-Hua Cheng: Power-Management Scheduling for Peak Power Minimization. J. Inf. Sci. Eng. 24(6): 1647-1668 (2008)
	2007
35		Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh: Clock Period Minimization with Minimum Delay Insertion. DAC 2007: 970-975
34		Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang: A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. EUC 2007: 507-516
33		Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng: Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. EUC Workshops 2007: 638-647
32		Shih-Hsu Huang, Yow-Tyng Nieh: Clock skew scheduling with race conditions considered. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
31		Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu: Opposite-Phase Clock Tree for Peak Current Reduction. IEICE Transactions 90-A(12): 2727-2735 (2007)
30		Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh: A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. J. Inf. Sci. Eng. 23(6): 1681-1705 (2007)
	2006
29		Shih-Hsu Huang, Chun-Hua Cheng: Operation Scheduling for False Loop Free Circuits. APCCAS 2006: 1619-1622
28		Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang: Peak Power Minimization through Power Management Scheduling. APCCAS 2006: 868-871
27		Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh: Fast multi-domain clock skew scheduling for peak current reduction. ASP-DAC 2006: 254-259
26		Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu: Register binding for clock period minimization. DAC 2006: 439-444
25		Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh: State re-encoding for peak current minimization. ICCAD 2006: 33-38
24		Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang: An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. JCIS 2006
23		Shih-Hsu Huang, Shi-Zhi Liu, Yi-Rung Chen, Jian-Yuan Lai: High-Speed Fuzzy Inference Processor Using Active Rules Identification. JCIS 2006
22		Shih-Hsu Huang, Yow-Tyng Nieh: Synthesis of nonzero clock skew circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 961-976 (2006)
21		Shih-Hsu Huang, Chun-Hua Cheng: An ILP Approach to the Slack Driven Scheduling Problem. IEICE Transactions 89-A(6): 1852-1858 (2006)
	2005
20		Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu: Minimizing peak current via opposite-phase clock tree. DAC 2005: 182-185
19		Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu: Race-condition-aware clock skew scheduling. DAC 2005: 475-478
18		Shih-Hsu Huang, Yi-Rung Chen: VLSI implementation of type-2 fuzzy inference processor. ISCAS (4) 2005: 3307-3310
17		Shih-Hsu Huang, Chun-Hua Cheng: A formal approach to the slack driven scheduling problem in high-level synthesis. ISCAS (6) 2005: 5633-5636
16		Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh: Floorplanning with clock tree estimation. ISCAS (6) 2005: 6244-6247
15		Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng: Three-dimension scheduling under multi-cycle interconnect communications. IEICE Electronic Express 2(4): 108-114 (2005)
14		Shih-Hsu Huang, Jian-Yuan Lai: A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities. IEICE Transactions 88-D(10): 2410-2416 (2005)
13		Shih-Hsu Huang, Jian-Yuan Lai: High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions. J. Inf. Sci. Eng. 21(3): 607-626 (2005)
	2004
12		Shih-Hsu Huang, Yi-Siang Hsu, Chiu-Cheng Lin: A Timing Driven Crosstalk Optimizer for Gridded Channel Routing. IEICE Transactions 87-D(6): 1575-1581 (2004)
	2003
11		Shih-Hsu Huang, Yow-Tyng Nieh: Clock Period Minimization of Non-Zero Clock Skew Circuits. ICCAD 2003: 809-812
	2002
10		Shih-Hsu Huang, Yi-Siang Hsu: A timing driven approach for crosstalk minimization in gridded channel routing. APCCAS (1) 2002: 263-266
9		Shih-Hsu Huang, Wen-Hon Peng, Jian-Yuan Lai: Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions. APCCAS (2) 2002: 43-46
8		Shih-Hsu Huang, Chu-Liao Wang: An effective floorplan-based power distribution network design methodology under reliability constraints. ISCAS (1) 2002: 353-356
	2001
7		Shih-Hsu Huang, Jian-Yuan Lai: A High Speed VLSI Fuzzy Logic Controller With Pipeline Architecture. FUZZ-IEEE 2001: 1054-1057
6		Shih-Hsu Huang: An effective low power design methodology based on interconnect prediction. SLIP 2001: 189-194
	2000
5		Mely Chen Chi, Shih-Hsu Huang: A Reliable Clock Tree Design Methodology for ASIC Designs. ISQED 2000: 269-274
	1995
4		Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang: Synthesis of false loop free circuits. ASP-DAC 1995
3		Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang: A new approach to schedule operations across nested-ifs and nested-loops. Microprocessing and Microprogramming 41(1): 37-52 (1995)
2		Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang: A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits. Microprocessing and Microprogramming 41(7): 501-519 (1995)
	1992
1		Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang: A new approach to schedule operations across nested-ifs and nested-loops. MICRO 1992: 268-271

Coauthor Index

1	Chia-Ming Chang	[24] [25] [27] [28] [30] [35] [38] [42] [46]
2	Yi-Rung Chen	[18] [23]
3	Chun-Hua Cheng	[15] [17] [21] [24] [26] [28] [29] [33] [35] [36] [37] [39] [40] [41] [43] [44] [45] [47] [50]
4	Mely Chen Chi	[5]
5	Chung-Hsin Chiang	[15] [24] [28]
6	Yuan-Kai Ho	[38]
7	Tsai-Ming Hsieh	[16]
8	Sheng-Yu Hsu	[20] [31]
9	Yi-Siang Hsu	[10] [12]
10	Yu-Chin Hsu	[1] [2] [3] [4]
11	Man-Lin Huang	[34]
12	Wei-Lun Huang	[48]
13	Cheng-Tsung Hwang	[1] [3]
14	Guan-Yu Jhuo	[48]
15	Jian-Yuan Lai	[7] [9] [13] [14] [23]
16	Chih-Hung Lee	[16] [47]
17	Yen-Hsin Lee	[49]
18	Chih-Yuan Lin	[16]
19	Chiu-Cheng Lin	[12]
20	Jia-Zong Lin	[38]
21	Shi-Zhi Liu	[23]
22	Ta-Yung Liu	[4]
23	Feng-Pin Lu	[19]
24	Yu-Sheng Lu	[38]
25	Yow-Tyng Nieh	[11] [19] [20] [22] [25] [26] [27] [30] [31] [32] [35] [42]
26	Yen-Jen Oyang	[1] [2] [3] [4]
27	Song-Bin Pan	[40] [46]
28	Wen-Hon Peng	[9]
29	Chin-Hung Su	[16]
30	Wen-Pin Tu	[46] [49] [50]
31	Da-Chen Tzeng	[39]
32	Chu-Liao Wang	[8] [34]
33	Hsin-Po Wang	[38]
34	Jheng-Fu Yeh	[43]
35	Wei-Ting Yen	[33]
36	Wei-Chieh Yu	[26]

Colors in the list of coauthors

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