Shi-Yu Huang

	2012
53		Feng-Cheng Huang, Shi-Yu Huang, Ji-Wei Ker, Yung-Chang Chen: High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction. IEEE Trans. Circuits Syst. Video Techn. 22(3): 340-351 (2012)
	2011
52		Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh: PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. DAC 2011: 47-52
51		Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chiou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang: A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776
50		Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen: Black-box leakage power modeling for cell library and SRAM compiler. DATE 2011: 637-642
49		Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao: A fully cell-based design for timing measurement of memory. ITC 2011: 1-10
48		Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu: Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores. IEEE Design & Test of Computers 28(4): 88-97 (2011)
47		Hsuan-Jung Hsu, Shi-Yu Huang: A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme. IEEE Trans. VLSI Syst. 19(1): 165-170 (2011)
46		Cheng-Hung Lo, Shi-Yu Huang: P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation. J. Solid-State Circuits 46(3): 695-704 (2011)
	2010
45		Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang: PAC duo system power estimation at ESL. ASP-DAC 2010: 815-820
44		Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu: Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium 2010: 389-394
43		Cheng-Yen Lin, Po-Yu Chen, Chun-Kai Tseng, Chung-Wen Huang, Chia-Chieh Weng, Chi-Bang Kuan, Shih-Han Lin, Shi-Yu Huang, Jenq Kuen Lee: Power aware SID-based simulator for embedded multicore DSP subsystems. CODES+ISSS 2010: 95-104
42		Chao-Wen Tzeng, Shi-Yu Huang: Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 834-839 (2010)
	2009
41		Chao-Wen Tzeng, Shi-Yu Huang: QC-Fill: An X-Fill method for quick-and-cool scan test. DATE 2009: 1142-1147
40		Chao-Wen Tzeng, Shi-Yu Huang: QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1756-1766 (2009)
39		Chao-Wen Tzeng, Han-Chia Cheng, Shi-Yu Huang: Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 764-769 (2009)
	2008
38		Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang: A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
37		Chao-Wen Tzeng, Shi-Yu Huang: UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. IEEE Design & Test of Computers 25(2): 132-140 (2008)
36		Ya-Chun Lai, Shi-Yu Huang: A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design. IEEE Trans. on Circuits and Systems 55-II(10): 1031-1035 (2008)
	2007
35		Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang: RT-level vector selection for realistic peak power simulation. ACM Great Lakes Symposium on VLSI 2007: 576-581
34		Chao-Wen Tzeng, J.-J. Hsu, Shi-Yu Huang: Robust paradigm for diagnosing hold-time faults in scan chains. IET Computers & Digital Techniques 1(6): 706-715 (2007)
	2006
33		Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang: A network security processor design based on an integrated SOC design and test platform. DAC 2006: 490-495
32		Yu-Chiun Lin, Shi-Yu Huang: Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults. J. Electronic Testing 22(2): 151-159 (2006)
	2005
31		Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang: Power estimation starategies for a low-power security processor. ASP-DAC 2005: 367-371
30		Jheng-Syun Yang, Shi-Yu Huang: Quick Scan Chain Diagnosis Using Signal Profiling. ICCD 2005: 157-160
	2004
29		Shi-Yu Huang: A Fading Algorithm For Sequential Fault Diagnosis. DFT 2004: 139-147
	2003
28		Yu-Chiun Lin, Shi-Yu Huang: Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. Asian Test Symposium 2003: 38-43
27		MingHung Lee, TingTing Hwang, Shi-Yu Huang: Decomposition of Extended Finite State Machine for Low Power Design. DATE 2003: 11152-11153
26		Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang: Combinational circuit fault diagnosis using logic emulation. ISCAS (5) 2003: 549-552
25		Shi-Yu Huang: A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis. J. Electronic Testing 19(2): 161-172 (2003)
24		Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu: Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. J. Inf. Sci. Eng. 19(4): 571-587 (2003)
	2002
23		Shi-Yu Huang: Diagnosis Of Byzantine Open-Segment Faults. Asian Test Symposium 2002: 248-
22		Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang: Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. DFT 2002: 117-128
21		Shi-Yu Huang: Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. VTS 2002: 193-200
	2001
20		Shi-Yu Huang: Towards the logic defect diagnosis for partial-scan designs. ASP-DAC 2001: 313-318
19		Shi-Yu Huang: On speeding up extended finite state machines using catalyst circuitry. ASP-DAC 2001: 583-588
18		Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang: A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103-
17		Shi-Yu Huang: On Improving the Accuracy Of Multiple Defect Diagnosis. VTS 2001: 34-41
16		Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. 6(2): 244-275 (2001)
	2000
15		Shi-Yu Huang, Sudhakar M. Reddy: High Performance/Delay Testing. Asian Test Symposium 2000: 490-
14		Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer: AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000)
	1999
13		Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai: Fault emulation: A new methodology for fault grading. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1487-1495 (1999)
12		Shi-Yu Huang, Kwang-Ting Cheng: ErrorTracer: design error diagnosis based on fault simulation techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1341-1352 (1999)
11		Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1376-1384 (1999)
	1998
10		Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho: A Hybrid Power Model for RTL Power Estimation. ASP-DAC 1998: 551-556
9		Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu: Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC 1998: 632-637
	1997
8		Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng: Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC 1997: 974-981
7		Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Incremental logic rectification. VTS 1997: 143-149
	1996
6		Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee: Compact Vector Generation for Accurate Power Simulation. DAC 1996: 161-164
5		Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Error Correction Based on Verification Techniques. DAC 1996: 258-261
4		Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI 1996: 277-
3		Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee: A novel methodology for transistor-level power estimation. ISLPED 1996: 67-72
2		Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser: An ATPG-Based Framework for Verifying Sequential Equivalence. ITC 1996: 865-874
	1995
1		Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai: Fault emulation: a new approach to fault grading. ICCAD 1995: 681-686

Coauthor Index

1	Jenn-Chiou Bor	[51]
2	Forrest Brewer	[14]
3	Ken-Feng Chang	[26]
4	Shih-Chieh Chang	[31]
5	Shu-Lin Chang	[51]
6	Tien-Yu Chang	[51]
7	Wen-Feng Chang	[24]
8	Yi-Chung Chang	[49]
9	I-Ling Chen	[31]
10	Ji-Jan Chen	[50]
11	Jian-Long Chen	[26]
12	Kuang-Chien Chen	[2] [3] [4] [5] [6] [7] [8] [9] [11] [14] [16]
13	Po-Yu Chen	[43]
14	Yin Chen	[48]
15	Yung-Chang Chen	[53]
16	David Ihsin Cheng	[8]
17	Han-Chia Cheng	[39]
18	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [16]
19	Chun-Chuan Chi	[51]
20	Yung-Fa Chou	[44]
21	Ming-Yi Chu	[51]
22	Wei-Jin Dai	[1] [13]
23	Li-Ming Denq	[51]
24	Shan-Chien Fang	[50] [52]
25	Uwe Gläser	[2]
26	ChingYen Ho	[10]
27	Wen-Tsan Hsieh	[45] [52]
28	Chen-Wei Hsu	[52]
29	Hsuan-Jung Hsu	[47] [51]
30	J.-J. Hsu	[34]
31	Sheng-Yu Hsu	[31]
32	Chih-Tsun Huang	[18] [33] [51]
33	Chung-Wen Huang	[43]
34	Chung-Yang Huang (Chung-Yang (Ric) Huang)	[14]
35	Feng-Cheng Huang	[53]
36	Jing-Reng Huang	[22]
37	Po-Chiun Huang	[51]
38	TingTing Hwang	[27]
39	Yi-Min Jiang	[10]
40	Hong-Chou Kao	[24]
41	Ji-Wei Ker	[53]
42	Chi-Bang Kuan	[43]
43	Yung-Sheng Kuo	[51]
44	Ding-Ming Kwai	[44]
45	Ya-Chun Lai	[36]
46	Chi-Ying Lee	[51]
47	Jenq Kuen Lee	[43]
48	Mike Tien-Chien Lee	[3]
49	Min-Sheng Lee	[33]
50	MingHung Lee	[27]
51	Tien-Chien Lee	[6]
52	Yen-Fong Lee	[31]
53	Chin-Fu Li	[51]
54	Jia-Lu Liao	[52]
55	Cheng-Yen Lin	[43]
56	Jian-Cheng Lin	[31]
57	Shih-Han Lin	[43]
58	Shyh-Horng Lin	[18]
59	Yu-Chiun Lin	[28] [32]
60	Jing-Jia Liou	[51]
61	Cheng-Hung Lo	[46]
62	Chih-Yen Lo	[33]
63	Juin-Yeu Joseph Lu	[9]
64	Shyue-Kung Lu	[24] [26] [48]
65	Hsi-Pin Ma	[51]
66	Sudhakar M. Reddy	[15]
67	Cheng-Tao Shieh	[31]
68	Ching-Cheng Tien	[51]
69	Ming-Fu Tsai	[24]
70	Chun-Kai Tseng	[43] [50]
71	Chao-Wen Tzeng	[34] [37] [38] [39] [40] [41] [42] [49]
72	Ruey-Shing Tzeng	[18]
73	Chen-Hsing Wang	[33] [51]
74	Chi-Hu Wang	[51]
75	Chih-Wea Wang	[18]
76	Deborah C. Wang	[10]
77	Horng-Bin Wang	[22]
78	Hsin-Po Wang	[18]
79	Chia-Chien Weng (Chia-Chieh Weng)	[35] [43] [50] [52]
80	Cheng Wu	[48]
81	Cheng-Wen Wu	[18] [24] [26] [33] [44] [51]
82	Chi-Feng Wu	[18]
83	Ching-Shang Yang	[35]
84	Jheng-Syun Yang	[30] [38]
85	Jack T. Yao	[49]
86	Jen-Chieh Yeh	[33] [45] [52]
87	Jhih-Wei You	[44]

Colors in the list of coauthors

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page