Po-Tsang Huang

	2012
16		Po-Tsang Huang, Wei Hwang: Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. J. Electrical and Computer Engineering 2012: (2012)
	2011
15		Po-Tsang Huang, Yung Chang, Wei Hwang: On-demand memory sub-system for multi-core SoCs. SoCC 2011: 122-127
14		Po-Tsang Huang, Wei Hwang: Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. IEICE Transactions 94-A(11): 2412-2424 (2011)
13		Po-Tsang Huang, Wei Hwang: A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. J. Solid-State Circuits 46(2): 507-519 (2011)
	2010
12		Hsin Rau, Chien-Hung Wu, Wei-Jung Shiang, Po-Tsang Huang: A decision support system of statistical process control for printed circuit boards manufacturing. ICMLC 2010: 2454-2458
11		Tien-Hung Lin, Po-Tsang Huang, Wei Hwang: Power noise suppression technique using active decoupling capacitor for TSV 3D integration. SoCC 2010: 209-212
10		Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang: A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electronics 6(4): 551-562 (2010)
	2009
9		Po-Tsang Huang, Wei Hwang: An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. SoCC 2009: 375-378
	2008
8		Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang: "Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS 2008: 3322-3325
7		Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang: A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS 2008: 3342-3345
6		Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang: Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS 2008: 77-83
5		Mu-Tien Chang, Po-Tsang Huang, Wei Hwang: A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC 2008: 175-178
	2007
4		Mu-Tien Chang, Po-Tsang Huang, Wei Hwang: A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC 2007: 207-210
	2006
3		Po-Tsang Huang, Wei-Keng Chang, Wei Hwang: Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS 2006: 1301-1304
2		Jen-Wei Yang, Po-Tsang Huang, Wei Hwang: On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS 2006: 666-669
1		Po-Tsang Huang, Wei Hwang: 2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS 2006

Coauthor Index

1	Hsie-Chia Chang	[10]
2	Ming-Hung Chang	[7]
3	Mu-Tien Chang	[4] [5]
4	Shu-Wei Chang	[8]
5	Wei-Keng Chang	[3]
6	Yung Chang	[15]
7	Li-Pu Chuang	[7]
8	Wei-Li Fang	[6]
9	Wei Hwang	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] [16]
10	Chih-Hao Kan	[7]
11	Chen-Yi Lee	[10]
12	Xin-Ru Lee	[10]
13	Tien-Hung Lin	[11]
14	Wen-Yen Liu	[8]
15	Hsin Rau	[12]
16	Wei-Jung Shiang	[12]
17	Yin-Ling Wang	[6]
18	Chien-Hung Wu	[12]
19	Jen-Wei Yang	[2]

Colors in the list of coauthors

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