Ming-Ching Huang

	2006
1		Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang: Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. ISCAS 2006

Coauthor Index

1	Yen-Hsiang Chen	[1]
2	Chia-Fang Lee	[1]
3	Jin-Tai Yan	[1]

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page