Li-Da Huang

	2009
14		Bo-Zhou Chen, Hung-Ming Chen, Li-Da Huang, Po-Cheng Pan: A stochastic-based efficient critical area extractor on OpenAccess platform. ACM Great Lakes Symposium on VLSI 2009: 197-202
	2008
13		Lun-Chun Wei, Hung-Ming Chen, Li-Da Huang, Sarah Songjie Xu: Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow. ACM Great Lakes Symposium on VLSI 2008: 359-362
	2007
12		Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong: OPC-Friendly Bus Driven Floorplanning. ISQED 2007: 847-852
11		Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu: Using power gating techniques in area-array SoC floorplan design. SoCC 2007: 233-236
	2005
10		Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong: Redundant-via enhanced maze routing for yield improvement. ASP-DAC 2005: 1148-1151
9		Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong: Simultaneous power supply planning and noise avoidance in floorplan design. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 578-587 (2005)
	2004
8		Li-Da Huang, Martin D. F. Wong: Optical proximity correction (OPC): friendly maze routing. DAC 2004: 186-191
7		Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang: I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ICCD 2004: 562-567
6		Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu: A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 141-147 (2004)
	2003
5		Li-Da Huang, Hung-Ming Chen, D. F. Wong: Global Wire Bus Configuration with Minimum Delay Uncertainty. DATE 2003: 10050-10055
4		Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee: Explicit gate delay model for timing evaluation. ISPD 2003: 32-38
3		Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao: Maze routing with buffer insertion under transition time constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 91-95 (2003)
	2002
2		Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu: A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE 2002: 470-475
1		Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao: Maze Routing with Buffer Insertion under Transition Time Constraints. DATE 2002: 702-707

Coauthor Index

1	Huijing Cao	[4]
2	Bo-Zhou Chen	[14]
3	Hung-Ming Chen	[5] [7] [9] [11] [13] [14]
4	Liang Deng	[12]
5	Youxin Gao	[1] [3] [4]
6	Minghorng Lai	[1] [3]
7	Seokjin Lee	[4]
8	Chien-Nan Jimmy Liu	[11]
9	I-Min Liu	[2] [6] [7] [9]
10	Chao-Hung Lu	[11]
11	David Z. Pan (David Zhigang Pan)	[10]
12	Po-Cheng Pan	[14]
13	Muzhou Shao	[4] [7]
14	Xiaoping Tang	[2] [6]
15	Lun-Chun Wei	[13]
16	Wei-Ting Wei	[11]
17	Martin D. F. Wong (D. F. Wong)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12]
18	Hua Xiang	[2] [6] [12]
19	Gang Xu	[10]
20	Sarah Songjie Xu	[13]
21	Chi-Yi Yeh	[11]
22	Li-Pen Yuan	[4]

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