Juinn-Dar Huang

	2012
30		Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang: Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only). FPGA 2012: 268
29		Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou: Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Transactions 95-A(2): 559-566 (2012)
	2011
28		Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: Equivalence checking of scheduling with speculative code transformations in high-level synthesis. ASP-DAC 2011: 497-502
27		Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho: Throughput optimization for latency-insensitive system with minimal queue insertion. ASP-DAC 2011: 585-590
26		Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang: Architectural exploration of 3D FPGAs towards a better balance between area and delay. DATE 2011: 587-590
25		Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang: Layer-Aware Design Partitioning for Vertical Interconnect Minimization. ISVLSI 2011: 144-149
24		Chia-I Chen, Juinn-Dar Huang: Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family. ISVLSI 2011: 369-370
23		Juinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu: Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture. IEICE Transactions 94-A(4): 1151-1155 (2011)
	2010
22		Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou: Expandable MDC-based FFT architecture and its generator for high-performance applications. SoCC 2010: 188-192
21		Chia-I Chen, Juinn-Dar Huang: A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication. IEICE Transactions 93-A(7): 1300-1308 (2010)
20		Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou: FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26(5): 1601-1617 (2010)
	2009
19		Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang: Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. ASP-DAC 2009: 19-24
18		Chia-I Chen, Juinn-Dar Huang: CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture. ASP-DAC 2009: 67-72
17		Yu-Ru Hong, Juinn-Dar Huang: Reducing fault dictionary size for million-gate large circuits. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
16		Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. IEEE Trans. VLSI Syst. 17(5): 723-727 (2009)
15		Ya-Shih Huang, Yu-Ju Hong, Juinn-Dar Huang: Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture. IEICE Transactions 92-A(12): 3143-3150 (2009)
	2008
14		Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang: A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. ASP-DAC 2008: 16-21
13		Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou: Verification of Pin-Accurate Port Connections. IEEE Design & Test of Computers 25(5): 478-486 (2008)
	2007
12		Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou: A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. ASP-DAC 2007: 165-170
11		Yu-Ru Hong, Juinn-Dar Huang: Fault Dictionary Size Reduction for Million-Gate Large Circuits. ASP-DAC 2007: 829-834
	2006
10		Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC 2006: 448-453
9		Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou: A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. ASP-DAC 2006: 600-605
	2004
8		Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang: Verification on Port Connections. ITC 2004: 830-836
	2001
7		Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. VLSI Syst. 9(2): 251-260 (2001)
	2000
6		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. VLSI Syst. 8(4): 392-400 (2000)
	1998
5		Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang: Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC 1998: 712-717
4		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang: On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. VLSI Syst. 6(4): 634-642 (1998)
	1996
3		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD 1996: 13-17
	1995
2		Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao: Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping. DAC 1995: 65-69
1		Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen: Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD 1995: 359-363

Coauthor Index

1	Han-Yuan Chang	[30]
2	Shih-Min Chao	[2]
3	Chia-I Chen	[18] [21] [23] [24] [26] [29]
4	Chien-Hua Chen	[9]
5	Yi-Hang Chen	[27]
6	Hsien-Ho Chuang	[4]
7	Ya-Chien Ho	[27]
8	Yu-Ju Hong	[15] [19]
9	Yu-Ru Hong	[11] [14] [17]
10	Mi-Yu Hsu	[30]
11	Wan-Ling Hsu	[23] [29]
12	Wei-Sheng Huang	[14]
13	Ya-Shih Huang	[14] [15] [19] [25] [30]
14	Jie-Hong Roland Jiang (Jie-Hong R. Jiang)	[5] [7]
15	Jing-Yang Jou	[1] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [16] [20] [22] [28] [29]
16	Bau-Cheng Lee	[26]
17	Chi-Hui Lee	[28]
18	Geeng-Wei Lee	[8] [9] [12] [13]
19	Bu-Ching Lin	[12] [22]
20	Yen-Ting Lin	[23] [29]
21	Yang-Hsiang Liu	[25]
22	Wen-Zen Shen	[1] [2] [3] [4] [6]
23	Che-Hua Shih	[10] [16] [20] [28]
24	Man-Yun Su	[10]
25	Chun-Yao Wang	[8] [13]
26	Yu-Hsiang Wang	[22]
27	Ya-Ching Yang	[20]
28	Chia-Chih Yen	[20]

Colors in the list of coauthors

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page