 | 2011 |
| 8 |  | Hsin-Hsiung Huang,
Jui-Hung Hung,
Cheng-Chiang Lin,
Tsai-Ming Hsieh:
Wire Planning for Electromigration and Interference Avoidance in Analog Circuits.
IEICE Transactions 94-A(11): 2402-2411 (2011) |
| 7 |  | Hsin-Hsiung Huang,
Yi-Ren Yeh:
An iterative algorithm for robust kernel principal component analysis.
Neurocomputing 74(18): 3921-3930 (2011) |
| 2010 |
| 6 |  | Hsi-An Chien,
Cheng-Chiang Lin,
Hsin-Hsiung Huang,
Tsai-Ming Hsieh:
Optimal Supply Voltage Assignment under Timing, Power and Area Constraints.
IEICE Transactions 93-A(4): 761-768 (2010) |
| 2008 |
| 5 |  | Hsin-Hsiung Huang,
Hui-Yu Huang,
Yu-Cheng Lin,
Tsai-Ming Hsieh:
Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system.
ISCAS 2008: 1200-1203 |
| 4 |  | Hsin-Hsiung Huang,
Shu-Ping Chang,
Yu-Cheng Lin,
Tsai-Ming Hsieh:
Timing-driven X-architecture router among rectangular obstacles.
ISCAS 2008: 1804-1807 |
| 2006 |
| 3 |  | Hsin-Hsiung Huang,
Yung-Ching Chen,
Tsai-Ming Hsieh:
A congestion-driven buffer planner with space reservation.
ISCAS 2006 |
| 2005 |
| 2 |  | Chin-Hui Wang,
Yung-Ching Chen,
Tsai-Ming Hsieh,
Chih-Hung Lee,
Hsin-Hsiung Huang:
A new congestion and crosstalk aware router.
ISCAS (6) 2005: 6234-6237 |
| 2002 |
| 1 |  | Chih-Hung Lee,
Yu-Chung Lin,
Hsin-Hsiung Huang,
Tsai-Ming Hsieh:
Structural Decomposition with Functional Considerations for Low Power.
ISQED 2002: 464-469 |