Hong-Yi Huang

	2012
32		Hong-Yi Huang, Shiun-Dian Jan, Yang Chou, Cheng-Yu Chen: CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes. IEICE Transactions 95-C(2): 275-283 (2012)
	2011
31		Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo: All digital phase-locked loop using active inductor oscillator and novel locking algorithm. ISCAS 2011: 486-489
30		Shih-Lun Chen, Hong-Yi Huang, Ching-Hsing Luo: A Low-Cost High-Quality Adaptive Scalar for Real-Time Multimedia Applications. IEEE Trans. Circuits Syst. Video Techn. 21(11): 1600-1611 (2011)
29		Shih-Lun Chen, Hong-Yi Huang, Ching-Hsing Luo: Time Multiplexed VLSI Architecture for Real-Time Barrel Distortion Correction in Video-Endoscopic Images. IEEE Trans. Circuits Syst. Video Techn. 21(11): 1612-1621 (2011)
28		Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu: A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. IEEE Trans. on Circuits and Systems 58-II(8): 492-496 (2011)
27		Hong-Yi Huang, Ruei-Iun Pu: Differential bidirectional transceiver for on-chip long wires. Microelectronics Journal 42(11): 1208-1215 (2011)
	2010
26		Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang: A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS 2010: 285-288
25		Shiann-Rong Kuang, Jiun-Ping Wang, Hong-Yi Huang: Variable-Latency Floating-Point Multipliers for Low-Power Applications. IEEE Trans. VLSI Syst. 18(10): 1493-1497 (2010)
	2009
24		Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng: 0.5V 160-MHz 260uW all digital phase-locked loop. DDECS 2009: 186-193
23		Hong-Yi Huang, Fu-Chien Tsai: Analysis and optimization of ring oscillator using sub-feedback scheme. DDECS 2009: 28-29
22		Shih-Lun Chen, Ho-Yin Lee, Chiung-An Chen, Hong-Yi Huang, Ching-Hsing Luo: Wireless Body Sensor Network With Adaptive Low-Power Design for Biometrics and Healthcare Applications. IEEE Systems Journal 3(4): 398-409 (2009)
	2008
21		Wei-Chen Huang, Chen-Ming Hsu, Chien-Ming Lee, Hong-Yi Huang, Ching-Hsing Luo: Dual band LNA/mixer using conjugate matching for implantable biotelemetry. ISCAS 2008: 1764-1767
20		Hong-Yi Huang, Chia-Ming Liang, Shi-Jia Sun: Low-power 50% duty cycle corrector. ISCAS 2008: 2362-2365
19		Hong-Yi Huang, Li-Wei Huang, Wei-Sheng Tseng, Chih-Yuan Hsu: A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator. SoCC 2008: 333-336
18		Hong-Yi Huang, Yi-Jui Tsai, Kung-Liang Ho, Chan-Yu Lin: All digital time-to-digital converter using single delay-locked loop. SoCC 2008: 341-344
	2007
17		Hong-Yi Huang, Sheng-Da Wu, Yi-Jui Tsai: A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme. ISCAS 2007: 2160-2163
	2006
16		Hong-Yi Huang, Chia-Ming Liang, Wei-Ming Chiu: 1-99% input duty 50% output duty cycle corrector. ISCAS 2006
15		Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu: High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit. ISCAS 2006
14		Hong-Yi Huang, Ching-Chieh Wu, Sen-Da Wu: On-chip bidirectional transceiver. ISCAS 2006
	2005
13		Hong-Yi Huang, Sheng-Fen Ho, Li-Wei Huang: A 64-MHz/spl sim/1920-MHz programmable spread-spectrum clock generator. ISCAS (4) 2005: 3363-3366
	2004
12		Chun-Jen Huang, Hong-Yi Huang: A low-voltage CMOS rail-to-rail operational amplifier using double p-channel differential input pairs. ISCAS (1) 2004: 673-676
11		Hong-Yi Huang, Shih-Lun Chen: Interconnect accelerating techniques for sub-100-nm gigascale systems. IEEE Trans. VLSI Syst. 12(11): 1192-1200 (2004)
	2003
10		Chin-Shan Hsieh, Hong-Yi Huang, Jeng-Dang Juan, Ruey-Nan Yeh: A high-bandwidth wireless infrared receiver with feedforward offset extractor. ISCAS (1) 2003: 73-76
	2002
9		Hong-Yi Huang, Jing-Fu Lin: Multiple bulk input differential logic. APCCAS (1) 2002: 461-464
8		Hong-Yi Huang, Shih-Lun Chen: Threshold triggers and accelerator for deep submicron interconnection. APCCAS (2) 2002: 143-146
7		Hong-Yi Huang, Jing-Fu Lin: CMOS bulk input technique. ISCAS (3) 2002: 253-256
6		Hong-Yi Huang, Shih-Lun Chen: Input isolated sense amplifiers. ISCAS (4) 2002: 587-590
5		Hong-Yi Huang, Hsuan-Yi Su: Low-power 2P2N SRAM with column hidden refresh. ISCAS (4) 2002: 591-594
	2001
4		Hong-Yi Huang, Teng-Neng Wang: High-speed CMOS logic circuits in capacitor coupling technique. ISCAS (4) 2001: 634-637
	1995
3		Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu: Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS 1995: 1572-1575
	1994
2		Hong-Yi Huang, Chung-Yu Wu: New CMOS Differential Logic Circuits for True-Single-Phase Pipelined Systems. ISCAS 1994: 15-18
	1993
1		Hong-Yi Huang, Chung-Yu Wu: Redundant Algebra and Integrated Circuit Implementation of Ternary Logic and Their Applications. ISCAS 1993: 1905-1908

Coauthor Index

1	Cheng-Yu Chen	[32]
2	Chiung-An Chen	[22]
3	Shih-Lun Chen	[6] [8] [11] [22] [29] [30]
4	Kuo-Hsing Cheng	[3] [24] [26] [28] [31]
5	Wei-Ming Chiu	[16]
6	Yang Chou	[32]
7	Yuan-Hua Chu	[3]
8	Kung-Liang Ho	[18]
9	Sheng-Fen Ho	[13]
10	Chin-Shan Hsieh	[10]
11	Chen-Ming Hsu	[21]
12	Chih-Yuan Hsu	[19]
13	Chang-Chien Hu	[26]
14	Chun-Jen Huang	[12]
15	Li-Wei Huang	[13] [19]
16	Tzu-Chi Huang	[31]
17	Wei-Chen Huang	[21]
18	Shiun-Dian Jan	[32]
19	Yong-Jhen Jhu	[28]
20	Jeng-Dang Juan	[10]
21	Shiann-Rong Kuang	[25]
22	Chien-Ming Lee	[21]
23	Ho-Yin Lee	[22]
24	Yu-Liang Li	[28]
25	Chia-Ming Liang	[16] [20]
26	Chan-Yu Lin	[18]
27	Jing-Fu Lin	[7] [9]
28	Jen-Chieh Liu	[15] [24] [26] [28] [31]
29	Ching-Hsing Luo	[21] [22] [29] [30] [31]
30	Ruei-Iun Pu	[27]
31	Hsuan-Yi Su	[5]
32	Shi-Jia Sun	[20]
33	Fu-Chien Tsai	[23]
34	Yi-Jui Tsai	[17] [18]
35	Wei-Sheng Tseng	[19]
36	Bo-Ruei Wang	[15]
37	Jinn-Shyan Wang	[3]
38	Jiun-Ping Wang	[25]
39	Teng-Neng Wang	[4]
40	Ching-Chieh Wu	[14]
41	Chung-Yu Wu	[1] [2] [3]
42	Sen-Da Wu	[14]
43	Sheng-Da Wu	[17]
44	Tain-Shun Wu	[3]
45	Wei-Bin Yang	[24]
46	Ruey-Nan Yeh	[10]

Colors in the list of coauthors

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