Chih-Tsun Huang

	2011
44		Shuo-Hung Chen, Hsiao-Mei Lin, Ching-Chou Hsieh, Chih-Tsun Huang, Jing-Jia Liou, Yeh-Ching Chung: TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler. ASP-DAC 2011: 97-98
43		Shih-Liang Chen, Bo-Ru Ke, Jian-Nan Chen, Chih-Tsun Huang: Reliability analysis and improvement for multi-level non-volatile memories with soft information. DAC 2011: 753-758
42		Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chiou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang: A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776
41		Jyu-Yuan Lai, Chih-Tsun Huang: Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications. IEEE Trans. VLSI Syst. 19(8): 1512-1517 (2011)
	2010
40		Jyu-Yuan Lai, Tzu-Yu Hung, Kai-Hsiang Yang, Chih-Tsun Huang: High-performance architecture for Elliptic Curve Cryptography over binary field. ISCAS 2010: 3933-3936
39		Mao-Yin Wang, Chih-Pin Su, Chia-Lung Horng, Cheng-Wen Wu, Chih-Tsun Huang: Single- and Multi-core Configurable AES Architectures for Flexible Security. IEEE Trans. VLSI Syst. 18(4): 541-552 (2010)
	2009
38		Jyu-Yuan Lai, Chih-Tsun Huang: A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography. IEEE Trans. on Circuits and Systems 56-II(5): 394-398 (2009)
	2008
37		Ming-Chang Hsieh, Chih-Tsun Huang: An embedded infrastructure of debug and trace interface for the DSP platform. DAC 2008: 866-871
36		Jyu-Yuan Lai, Chih-Tsun Huang: Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography. IEEE Trans. VLSI Syst. 16(11): 1567-1580 (2008)
	2007
35		Shin-Yi Lin, Chih-Tsun Huang: A High-Throughput Low-Power AES Cipher for Network Applications. ASP-DAC 2007: 595-600
34		Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Denq, Chien-Jung Chiu, Young-Wey Li, Chieh-Ming Chang: A prototype of a wireless-based test system. SoCC 2007: 225-228
33		Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang: Optimization of Pattern Matching Circuits for Regular Expression on FPGA. IEEE Trans. VLSI Syst. 15(12): 1303-1310 (2007)
32		Yen-Lin Peng, Cheng-Wen Wu, Jing-Jia Liou, Chih-Tsun Huang: BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. IET Computers & Digital Techniques 1(6): 716-723 (2007)
	2006
31		Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang: A network security processor design based on an integrated SOC design and test platform. DAC 2006: 490-495
30		Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang: Optimization of regular expression pattern matching circuits on FPGA. DATE Designers' Forum 2006: 12-17
	2005
29		Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu: A configurable AES processor for enhanced security. ASP-DAC 2005: 361-366
28		Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu: Design and test of a scalable security processor. ASP-DAC 2005: 372-375
27		Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu: A BIST Scheme for FPGA Interconnect Delay Faults. VTS 2005: 201-206
	2004
26		Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu: An HMAC processor with integrated SHA-1 and MD5 algorithms. ASP-DAC 2004: 456-458
25		Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu: On Test and Diagnostics of Flash Memories. Asian Test Symposium 2004: 260-265
24		Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu: Failure Factor Based Yield Enhancement for SRAM Designs. DFT 2004: 20-28
23		Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu: An Application-Independent Delay Testing Methodology for Island-Style FPGA. DFT 2004: 478-486
22		Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee: An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222
	2003
21		Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu: FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD 2003: 595-598
20		Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang: Fault Pattern Oriented Defect Diagnosis for Memories. ITC 2003: 29-38
19		Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu: Test and Diagnosis of Word-Oriented Multiport Memories. VTS 2003: 248-253
18		Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu: Built-in redundancy analysis for memory yield improvement. IEEE Transactions on Reliability 52(4): 386-399 (2003)
	2002
17		Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356-
16		Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411-
15		Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu: Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA 2002: 137-141
14		Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu: Diagonal Test and Diagnostic Schemes for Flash Memorie. ITC 2002: 37-46
13		Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu: RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS 2002: 281-288
12		Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu: Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 480-490 (2002)
	2001
11		Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang: A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103-
10		Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu: Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium 2001: 91-96
9		Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu: Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC 2001: 301-306
8		Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu: March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC 2001: 758-767
	2000
7		Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu: A programmable built-in self-test core for embedded memories. ASP-DAC 2000: 11-12
6		Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai: BRAINS: A BIST Compiler for Embedded Memories. DFT 2000: 299-
5		Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu: Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD 2000: 468-471
4		Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu: Simulation-Based Test Algorithm Generation for Random Access Memories. VTS 2000: 291-296
	1999
3		Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu: RAMSES: A Fast Memory Fault Simulator. DFT 1999: 165-173
2		Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang: A Programmable BIST Core for Embedded DRAM. IEEE Design & Test of Computers 16(1): 59-70 (1999)
	1997
1		Chih-Tsun Huang, Cheng-Wen Wu: High-speed C-testable systolic array design for Galois-field inversion. ED&TC 1997: 342-346

Coauthor Index

1	Jenn-Chiou Bor	[42]
2	Chieh-Ming Chang	[34]
3	Shih-Chieh Chang	[30] [33]
4	Shu-Lin Chang	[42]
5	Tien-Yu Chang	[42]
6	Tsin-Yuan Chang	[2]
7	Jian-Nan Chen	[43]
8	Shih-Liang Chen	[43]
9	Shuo-Hung Chen	[44]
10	Ying-Yen Chen	[34]
11	Chuang Cheng	[6]
12	Kuo-Liang Cheng	[4] [5] [8] [9] [10] [12] [13] [15] [16] [17] [19] [20] [21] [22] [28]
13	Chun-Chuan Chi	[42]
14	Chien-Jung Chiu	[34]
15	Sau-Kwo Chiu	[14]
16	Yung-Fa Chou	[15] [20] [21]
17	Ming-Yi Chu	[42]
18	Yeh-Ching Chung	[44]
19	Li-Ming Denq	[22] [34] [42]
20	Chia-Lung Horng	[29] [39]
21	Ching-Chou Hsieh	[44]
22	Ming-Chang Hsieh	[37]
23	Yu-Tsao Hsing	[24]
24	Hsuan-Jung Hsu	[42]
25	Huan-Shan Hsu	[16]
26	Yueh-Chih Hsu	[34]
27	Chia-Ming Hsueh	[10]
28	Frank Huang	[20]
29	Jing-Reng Huang	[2] [6] [7] [10] [16] [17] [22]
30	Po-Chiun Huang	[42]
31	Rei-Fu Huang	[25]
32	Shi-Yu Huang	[11] [31] [42]
33	Shin-Wei Hung	[22]
34	Tzu-Yu Hung	[40]
35	Chang-Ping Jiang	[30] [33]
36	Bo-Ru Ke	[43]
37	Yung-Sheng Kuo	[42]
38	Jyu-Yuan Lai	[36] [38] [40] [41]
39	Chi-Ying Lee	[42]
40	Jih-Nung Lee	[20] [21]
41	Jye-Yuan Lee	[22]
42	Min-Sheng Lee	[31]
43	Chin-Fu Li	[42]
44	Jin-Fu Li	[8] [18]
45	Young-Wey Li	[34]
46	Cheng-Hung Lin	[30] [33]
47	Hsiao-Mei Lin	[44]
48	Shin-Yi Lin	[35]
49	Shyh-Horng Lin	[11]
50	Yen-Fu Lin	[17]
51	Youn-Long Lin	[16] [17]
52	Jing-Jia Liou	[23] [27] [32] [34] [42] [44]
53	Chih-Yen Lo	[22] [31]
54	Hsi-Pin Ma	[34] [42]
55	Yen-Lin Peng	[23] [27] [32]
56	Yuan-Yuan Shih	[25]
57	Chih-Pin Su	[26] [28] [29] [39]
58	Ching-Cheng Tien	[34] [42]
59	Ming-Chang Tsai	[6]
60	Ruey-Shing Tzeng	[11]
61	Chen-Hsing Wang	[28] [31] [42]
62	Chi-Hu Wang	[34] [42]
63	Chih-Wea Wang	[5] [9] [11] [13] [16] [17] [19] [20] [21] [22] [24]
64	Chun-Chieh Wang	[27]
65	Hsin-Po Wang	[11]
66	Mao-Yin Wang	[26] [39]
67	Chen-Jong Wey	[6]
68	Cheng-Wen Wu	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [23] [24] [25] [26] [27] [28] [29] [31] [32] [34] [39] [42]
69	Chi-Feng Wu	[2] [3] [4] [5] [9] [11] [12] [15] [18]
70	Ching-Wei Wu	[24]
71	Hong-Tzer Yang	[20]
72	Kai-Hsiang Yang	[40]
73	Jen-Chieh Yeh	[10] [13] [14] [15] [25] [31]

Colors in the list of coauthors

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page