Chan-Wei Huang

	2009
3		Shu-Yu Jiang, Chan-Wei Huang, Yu-lung Lo, Kuo-Hsing Cheng: Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System. IEICE Transactions 92-A(2): 389-400 (2009)
	2006
2		Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang: Self-sampled vernier delay line for built-in clock jitter measurement. ISCAS 2006
	2004
1		Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang: 64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. IWSOC 2004: 65-68

Coauthor Index

1	Kuo-Hsing Cheng	[1] [2] [3]
2	Shun-Wen Cheng	[1]
3	Shu-Yu Jiang	[2] [3]
4	Yu-lung Lo	[3]

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page