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| 2004 | ||
|---|---|---|
| 1 | Pei-Yung Hsiao, Chun-Ho Hua, Chien-Chen Lin: A novel FPGA architectural implementation of pipelined thinning algorithm. ISCAS (2) 2004: 593-596 | |
| 1 | Pei-Yung Hsiao | [1] |
| 2 | Chien-Chen Lin | [1] |
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