Jiang Hu

	2012
135		Jiang Hu, Cheng-Kok Koh: International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012 ACM 2012
134		Jiang Hu, Cheng-Kok Koh: Guest Editorial Special Section on the 2011 International Symposium on Physical Design. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 165-166 (2012)
	2011
133		Yao-Wen Chang, Jiang Hu: Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011 ACM 2011
132		Muhammet Mustafa Ozdal, Steven Burns, Jiang Hu: Gate sizing and device technology selection algorithms for high-performance industrial designs. ICCAD 2011: 724-731
131		Yi-Le Huang, Jiang Hu, Weiping Shi: Lagrangian relaxation for gate implementation selection. ISPD 2011: 167-174
130		Xi Chen, Jiang Hu, Ning Xu: Regularity-constrained floorplanning for multi-core processors. ISPD 2011: 99-106
129		Kyu-Nam Shim, Jiang Hu: Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects. ISQED 2011: 80-86
128		Yimei Kang, Guan Wang, Jiang Hu: A mean shift based small target tracking algorithm in colored video. SoCPaR 2011: 407-412
127		Yifang Liu, Jiang Hu: GPU-Based Parallelization for Fast Circuit Optimization. ACM Trans. Design Autom. Electr. Syst. 16(3): 24 (2011)
126		Yifang Liu, Rupesh S. Shelar, Jiang Hu: Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 416-426 (2011)
125		Mohammad Asad R. Chaudhry, Zakia Asad, Alexander Sprintson, Jiang Hu: Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies. VLSI Design 2011: (2011)
	2010
124		Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar: Physical design techniques for optimizing RTA-induced variations. ASP-DAC 2010: 745-750
123		Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn: Detecting tangled logic structures in VLSI netlists. DAC 2010: 603-608
122		Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu: SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. DATE 2010: 1369-1372
121		Yifang Liu, Yu Yang, Jiang Hu: Clustering-based simultaneous task and voltage scheduling for NoC systems. ICCAD 2010: 277-283
120		Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li: Accurate clock mesh sizing via sequential quadraticprogramming. ISPD 2010: 135-142
119		Kyu-Nam Shim, Jiang Hu, José Silva-Martínez: A dual-level adaptive supply voltage system for variation resilience. ISQED 2010: 38-43
118		Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu: Useful clock skew optimization under a multi-corner multi-mode design framework. ISQED 2010: 62-68
117		Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li: Combinatorial Algorithms for Fast Clock Mesh Optimization. IEEE Trans. VLSI Syst. 18(1): 131-141 (2010)
116		Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. VLSI Syst. 18(12): 1639-1648 (2010)
115		Shiyan Hu, Patrik Shah, Jiang Hu: Pattern Sensitive Placement Perturbation for Manufacturability. IEEE Trans. VLSI Syst. 18(6): 1002-1006 (2010)
114		Rupak Samanta, Jiang Hu, Peng Li: Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks. IEEE Trans. VLSI Syst. 18(7): 1025-1035 (2010)
113		Yifang Liu, Jiang Hu: A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 223-234 (2010)
112		Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu: Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1342-1353 (2010)
	2009
111		Pratik J. Shah, Jiang Hu: Impact of lithography-friendly circuit layout. ACM Great Lakes Symposium on VLSI 2009: 385-388
110		Yifang Liu, Jiang Hu: GPU-based parallelization for fast circuit optimization. DAC 2009: 943-946
109		Yifang Liu, Jiang Hu: A new algorithm for simultaneous gate sizing and threshold voltage assignment. ISPD 2009: 27-34
108		Yang Liu, Tong Zhang, Jiang Hu: Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations. IEEE Trans. VLSI Syst. 17(3): 439-443 (2009)
107		Rupak Samanta, Ganesh Venkataraman, Jiang Hu: Clock Buffer Polarity Assignment for Power Noise Reduction. IEEE Trans. VLSI Syst. 17(6): 770-780 (2009)
106		Shiyan Hu, Mahesh Ketkar, Jiang Hu: Gate Sizing for Cell-Library-Based Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 28(6): 818-825 (2009)
105		Shiyan Hu, Jiang Hu: A fast general slew constrained minimum cost buffering algorithm. Microelectronics Journal 40(10): 1482-1486 (2009)
104		Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: A single layer zero skew clock routing in X architecture. Science in China Series F: Information Sciences 52(8): 1466-1475 (2009)
	2008
103		Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian: Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375
102		Sridhar Varadan, Janet Meiling Wang, Jiang Hu: Handling partial correlations in yield prediction. ASP-DAC 2008: 543-548
101		Nimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, Duncan Walker: Built-In Proactive Tuning System for Circuit Aging Resilience. DFT 2008: 96-104
100		Yifang Liu, Rupesh S. Shelar, Jiang Hu: Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD 2008: 101-106
99		Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Gate planning during placement for gated clock network. ICCD 2008: 128-133
98		Yifang Liu, Jiang Hu, Weiping Shi: Multi-scenario buffer insertion in multi-core processor designs. ISPD 2008: 15-22
97		Rupak Samanta, Jiang Hu, Peng Li: Discrete buffer and wire sizing for link-based non-tree clock networks. ISPD 2008: 175-181
96		Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Activity and register placement aware gated clock network design. ISPD 2008: 182-189
95		Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu: Elastic Timing Scheme for Energy-Efficient and Robust Performance. ISQED 2008: 537-542
94		Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu: Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED 2008: 627-632
93		Yifang Liu, Jiang Hu, Weiping Shi: Buffering Interconnect for Multicore Processor Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2183-2196 (2008)
92		Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen: Power Grid Analysis and Optimization Using Algebraic Multigrid. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 738-751 (2008)
91		Uday Padmanabhan, Janet Meiling Wang, Jiang Hu: Robust Clock Tree Routing in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1385-1397 (2008)
90		Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Low Power Gated Clock Tree Driven Placement. IEICE Transactions 91-A(2): 595-603 (2008)
89		Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integration 41(3): 426-438 (2008)
	2007
88		Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman: A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC 2007: 24-31
87		Jiang Hu, Andi Winterboer, Clifford Nass, Johanna D. Moore, Rebecca Illowsky: Context & usability testing: user-modeled information presentation in easy and difficult driving conditions. CHI 2007: 1343-1346
86		Shiyan Hu, Mahesh Ketkar, Jiang Hu: Gate Sizing For Cell Library-Based Designs. DAC 2007: 847-852
85		Shiyan Hu, Jiang Hu: Unified adaptivity optimization of clock and logic signals. ICCAD 2007: 125-130
84		Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen: Modeling, optimization and control of rotary traveling-wave oscillator. ICCAD 2007: 476-480
83		Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu: Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD 2007: 627-631
82		Andi Winterboer, Jiang Hu, Johanna D. Moore, Clifford Nass: The influence of user tailoring and cognitive load on user performance in spoken dialogue systems. INTERSPEECH 2007: 2717-2720
81		Shiyan Hu, Jiang Hu: Pattern sensitive placement for manufacturability. ISPD 2007: 27-34
80		Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi: An Efficient Algorithm for RLC Buffer Insertion. ISQED 2007: 171-175
79		Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED 2007: 299-304
78		Yang Liu, Tong Zhang, Jiang Hu: Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. ISQED 2007: 749-754
77		Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI 2007: 383-388
76		Ganesh Venkataraman, Jiang Hu: A Placement Methodology for Robust Clocking. VLSI Design 2007: 881-886
75		Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Utilizing Redundancy for Timing Critical Interconnect. IEEE Trans. VLSI Syst. 15(10): 1067-1080 (2007)
74		Ke Cao, Jiang Hu, Mosong Cheng: Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. IEEE Trans. VLSI Syst. 15(12): 1332-1340 (2007)
73		Ganesh Venkataraman, Jiang Hu, Frank Liu: Integrated Placement and Skew Optimization for Rotary Clocking. IEEE Trans. VLSI Syst. 15(2): 149-158 (2007)
72		Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin-Ngai Sze: Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007)
71		Bor-Yiing Su, Yao-Wen Chang, Jiang Hu: An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 719-733 (2007)
70		Chin-Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Path-Based Buffer Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1346-1355 (2007)
	2006
69		Mike Brzozowski, Kendra Carattini, Scott R. Klemmer, Patrick Mihelich, Jiang Hu, Andrew Y. Ng: groupTime: preference based group scheduling. CHI 2006: 1047-1056
68		Jamie Pearson, Jiang Hu, Holly P. Branigan, Martin J. Pickering, Clifford Nass: Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice. CHI 2006: 1177-1180
67		Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze: Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313
66		Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Steiner network construction for timing critical nets. DAC 2006: 379-384
65		Ke Cao, Sorin Dobre, Jiang Hu: Standard cell characterization considering lithography induced variations. DAC 2006: 801-804
64		Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze: Integrated placement and skew optimization for rotary clocking. DATE 2006: 756-761
63		Min-Seok Kim, Jiang Hu: Associative skew clock routing for difficult instances. DATE 2006: 762-767
62		Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen: Fast decap allocation based on algebraic multigrid. ICCAD 2006: 107-111
61		Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi: A new RLC buffer insertion algorithm. ICCAD 2006: 553-557
60		Rupak Samanta, Ganesh Venkataraman, Jiang Hu: Clock buffer polarity assignment for power noise reduction. ICCAD 2006: 558-562
59		Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li: Combinatorial algorithms for fast clock mesh optimization. ICCAD 2006: 563-567
58		Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu: High performance clock routing in X-architecture. ISCAS 2006
57		Uday Padmanabhan, Janet Meiling Wang, Jiang Hu: Statistical clock tree routing for robustness to process variations. ISPD 2006: 149-156
56		Bor-Yiing Su, Yao-Wen Chang, Jiang Hu: An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. ISPD 2006: 56-63
55		Cheng Zhuo, Jiang Hu, Kangsheng Chen: An Improved AMG-based Method for Fast Power Grid Analysis. ISQED 2006: 290-295
54		Zhuo Feng, Peng Li, Jiang Hu: Efficient Model Update for General Link-Insertion Networks. ISQED 2006: 43-50
53		Yang Liu, Tong Zhang, Jiang Hu: Low Power Trellis Decoder with Overscaled Supply Voltage. SiPS 2006: 205-208
52		Di Wu, Jiang Hu, Rabi N. Mahapatra: Antenna Avoidance in Layer Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 734-738 (2006)
51		Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006)
50		Anand Rajaram, Jiang Hu, Rabi N. Mahapatra: Reducing clock skew variability via crosslinks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1176-1182 (2006)
49		Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo: Analytical bound for unwanted clock skew due to wire width variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1869-1876 (2006)
	2005
48		Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra: Timing driven track routing considering coupling capacitance. ASP-DAC 2005: 1156-1159
47		Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18
46		Ke Cao, Puneet Dhawan, Jiang Hu: Library cell layout with Alt-PSM compliance and composability. ASP-DAC 2005: 216-219
45		Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Register placement for low power clock network. ASP-DAC 2005: 588-593
44		Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu: Skew scheduling and clock routing for improved tolerance to process variations. ASP-DAC 2005: 594-599
43		Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu: Clock network minimization methodology based on incremental placement. ASP-DAC 2005: 99-102
42		Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Navigating registers in placement for clock network minimization. DAC 2005: 176-181
41		Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Path based buffer insertion. DAC 2005: 509-514
40		Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra: DiCER: distributed and cost-effective redundancy for variation tolerance. ICCAD 2005: 393-397
39		Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert: Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596
38		QianYing Wang, Clifford Nass, Jiang Hu: Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences. INTERACT 2005: 106-116
37		Jiang Hu, Mike Brzozowski: Preference-Based Group Scheduling. INTERACT 2005: 990-993
36		Di Wu, Jiang Hu, Rabi N. Mahapatra: Coupling aware timing optimization and antenna avoidance in layer assignment. ISPD 2005: 20-27
35		Anand Rajaram, David Z. Pan, Jiang Hu: Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD 2005: 55-62
34		QianYing Wang, Jiang Hu, Clifford Nass: Natural Language Interface Put in Perspective: Interaction of Search Method and Task Complexity. NLUCS 2005: 3-12
33		Rishi Chaturvedi, Jiang Hu: An efficient merging scheme for prescribed skew clock routing. IEEE Trans. VLSI Syst. 13(6): 750-754 (2005)
32		Yongqiang Lu, Chin-Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Navigating Register Placement for Low Power Clock Network Design. IEICE Transactions 88-A(12): 3405-3411 (2005)
	2004
31		Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao: Layer assignment for crosstalk risk minimization. ASP-DAC 2004: 159-162
30		Cliff C. N. Sze, Jiang Hu, Charles J. Alpert: A place and route aware buffered Steiner tree construction. ASP-DAC 2004: 355-360
29		Anand Rajaram, Jiang Hu, Rabi N. Mahapatra: Reducing clock skew variability via cross links. DAC 2004: 18-23
28		Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay: Fast and flexible buffer trees that navigate the physical layout environment. DAC 2004: 24-29
27		V. Seth, Min Zhao, Jiang Hu: Exploiting level sensitive latches in wire pipelining. ICCAD 2004: 283-290
26		Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711
25		Rishi Chaturvedi, Jiang Hu: Buffered Clock Tree for High Quality IC Design. ISQED 2004: 381-386
24		Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004)
23		Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: A methodology for the simultaneous design of supply and signal networks. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1614-1624 (2004)
22		Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze: Porosity-aware buffered Steiner tree construction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 517-526 (2004)
	2003
21		Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu: Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. ICCAD 2003: 401-407
20		Rishi Chaturvedi, Jiang Hu: A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. ICCD 2003: 282-
19		Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay: Porosity aware buffered steiner tree construction. ISPD 2003: 158-165
18		Bing Lu, Jiang Hu, Gary Ellis, Haihua Su: Process variation aware clock tree routing. ISPD 2003: 174-181
17		Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham: Buffer insertion with adaptive blockage avoidance. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 492-498 (2003)
16		Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A practical methodology for early buffer and wire resource allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003)
	2002
15		Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: Congestion-driven codesign of power and signal networks. DAC 2002: 64-69
14		Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109
13		Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham: Buffer insertion with adaptive blockage avoidance. ISPD 2002: 92-97
12		Jiang Hu, Sachin S. Sapatnekar: A timing-constrained simultaneous global routing algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1025-1036 (2002)
	2001
11		Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194
10		Jiang Hu, Sachin S. Sapatnekar: Performance Driven Global Routing Through Gradual Refinement. ICCD 2001: 481-483
9		Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402
8		Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9
7		Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001)
6		Jiang Hu, Sachin S. Sapatnekar: A survey on multi-net global routing for integrated circuits. Integration 31(1): 1-49 (2001)
	2000
5		Jiang Hu, Sachin S. Sapatnekar: A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD 2000: 99-103
4		Jiang Hu, Sachin S. Sapatnekar: Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 446-458 (2000)
	1999
3		Jiang Hu, Sachin S. Sapatnekar: FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC 1999: 84-89
2		Jiang Hu, Sachin S. Sapatnekar: Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD 1999: 133-138
1		Huibo Hou, Jiang Hu, Sachin S. Sapatnekar: Non-Hanan routing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 436-444 (1999)

Coauthor Index

1	Charles J. Alpert	[7] [8] [9] [11] [13] [14] [16] [17] [19] [22] [24] [26] [28] [30] [39] [41] [47] [51] [67] [70] [72] [123]
2	Zakia Asad	[125]
3	Jinian Bian	[103]
4	Holly P. Branigan	[68]
5	Mike Brzozowski	[37] [69]
6	Steven Burns	[132]
7	Yici Cai	[32] [42] [43] [45] [58] [77] [79] [89] [90] [96] [99] [103] [104] [116] [118] [122]
8	Ke Cao	[46] [65] [74]
9	Kendra Carattini	[69]
10	Yao-Wen Chang	[56] [71] [133]
11	Rishi Chaturvedi	[20] [25] [33]
12	Mohammad Asad R. Chaudhry	[125]
13	Kangsheng Chen	[55] [62] [84] [92]
14	Wei Chen	[118]
15	Xi Chen	[130]
16	Mosong Cheng	[74]
17	Chris C. N. Chu (Chris Chu, Chris Chong-Nuen Chu)	[14] [24]
18	Puneet Dhawan	[46]
19	Sorin Dobre	[65]
20	Gary Ellis	[18]
21	Zhuo Feng	[54] [59] [117]
22	Gopal Gandham	[7] [9] [13] [14] [17] [19] [22] [24]
23	Wei Guo	[21] [49]
24	Xianlong Hong	[32] [42] [43] [45] [58] [77] [79] [89] [90] [96] [99] [103] [104] [116]
25	Huibo Hou	[1]
26	Milos Hrkic	[8] [14] [19] [22] [24] [28]
27	Shiyan Hu	[61] [66] [67] [72] [75] [80] [81] [85] [86] [105] [106] [115]
28	Liang Huang	[32] [42] [43] [45]
29	Yi-Le Huang	[131]
30	Rebecca Illowsky	[87]
31	Nikhil Jayakumar	[39]
32	Zhanyuan Jiang	[61] [80]
33	Tanuj Jindal	[123]
34	Andrew B. Kahng	[8] [88]
35	Yimei Kang	[128]
36	Shrirang K. Karandikar	[67] [72]
37	Chandramouli V. Kashyap	[14] [24]
38	Mahesh Ketkar	[86] [106]
39	Sunil P. Khatri	[39]
40	Min-Seok Kim	[63]
41	Scott R. Klemmer	[69]
42	Cheng-Kok Koh	[134] [135]
43	Peng Li	[39] [54] [59] [66] [75] [83] [94] [97] [112] [114] [117] [120]
44	Qiuyang Li	[66] [75]
45	Quiyang Li	[40]
46	Zhuo Li	[47] [61] [67] [72] [123]
47	John Lillis	[8]
48	Bao Liu	[8] [88]
49	Frank Liu	[64] [73] [124]
50	Yang Liu	[53] [78] [108]
51	Yifang Liu	[93] [98] [100] [109] [110] [113] [120] [121] [126] [127]
52	Bing Lu	[18] [21] [49] [58] [79] [89] [104]
53	Yongqiang Lu	[32] [42] [43] [45] [118]
54	Rabi N. Mahapatra	[21] [29] [31] [36] [40] [48] [49] [50] [52]
55	Patrick McGuinness	[39]
56	Venkata Rajesh Mekala	[120]
57	Patrick Mihelich	[69]
58	Johanna D. Moore	[82] [87]
59	Gi-Joon Nam	[123]
60	Clifford Nass	[34] [38] [68] [82] [87]
61	Sani R. Nassif	[15] [23]
62	José Luis Neves	[7] [9]
63	Andrew Y. Ng	[69]
64	Muhammet Mustafa Ozdal	[132]
65	Uday Padmanabhan	[57] [91]
66	David Z. Pan (David Zhigang Pan)	[35]
67	Rajendran Panda	[83] [94] [112]
68	Jamie Pearson	[68]
69	Martin J. Pickering	[68]
70	Stephen T. Quay	[7] [8] [9] [13] [14] [17] [19] [22] [24] [28]
71	Anand Rajaram	[21] [29] [35] [39] [49] [50]
72	Rupak Samanta	[60] [84] [95] [97] [101] [107] [114]
73	Sachin S. Sapatnekar	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [15] [16] [23] [26] [51] [124]
74	V. Seth	[27]
75	Nimay Shah	[95] [101]
76	Patrik Shah	[115]
77	Pratik J. Shah	[111]
78	Rupesh S. Shelar	[100] [126]
79	Weixiang Shen	[58] [77] [79] [89] [90] [96] [99] [104] [116] [118]
80	Weiping Shi	[41] [47] [61] [67] [70] [72] [80] [93] [98] [131]
81	Kyu-Nam Shim	[119] [129]
82	José Silva-Martínez	[119]
83	Alexander Sprintson (Alex Sprintson)	[125]
84	Bor-Yiing Su	[56] [71]
85	Haihua Su	[15] [18] [23]
86	A. J. Sullivan	[8]
87	Chin-Ngai Sze	[32] [70] [72]
88	Cliff C. N. Sze (Chin Ngai Sze, Cliff N. Sze)	[22] [26] [30] [41] [42] [44] [45] [47] [51] [64] [67]
89	Sridhar Varadan	[102]
90	Ganesh Venkataraman	[39] [40] [44] [59] [60] [64] [73] [76] [88] [95] [107] [117]
91	Paul G. Villarrubia (Paul Villarrubia)	[8] [11] [16]
92	Duncan Walker	[101]
93	Guan Wang	[128]
94	Janet Meiling Wang (Janet Meiling Wang Roveda)	[57] [91] [102]
95	QianYing Wang	[34] [38]
96	Yanfeng Wang	[103]
97	Yaoguang Wei	[124]
98	Charles B. Winn	[123]
99	Andi Winterboer	[82] [87]
100	Di Wu	[31] [36] [40] [48] [52]
101	Ning Xu	[130]
102	Xu Xu	[88]
103	Fan Yang	[122]
104	Yu Yang	[121]
105	Xiaoji Ye	[83] [94] [112] [120]
106	Huafeng Zhang	[84]
107	Ming Zhang	[101]
108	Tong Zhang	[53] [78] [108]
109	Min Zhao	[27] [31] [48] [62] [83] [92] [94] [112]
110	Qiang Zhou	[32] [42] [43] [45] [103] [118] [122]
111	Cheng Zhuo	[55] [62] [84] [92]

Colors in the list of coauthors

Last update Sat Jun 2 20:57:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page