 | 2012 |
| 6 |  | Alison Burdett,
Fu-Lung Hsueh:
Session 17 overview: Diagnostic and therapeutic technologies for health: Technology directions subcommittee.
ISSCC 2012: 290-291 |
| 2011 |
| 5 |  | Tzu-Chi Huang,
Wen-Shen Chou,
Yu-Huei Lee,
Yao-Yi Yang,
Ke-Horng Chen,
Yung-Chow Peng,
Fu-Lung Hsueh:
55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter.
ESSCIRC 2011: 383-386 |
| 2010 |
| 4 |  | W. M. Young,
Chua-Huang Huang,
Alan P. Su,
C. P. Jou,
Fu-Lung Hsueh:
A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example.
ASP-DAC 2010: 821-824 |
| 3 |  | Wei-Chih Chen,
Chien-Chun Tsai,
Chih-Hsien Chang,
Yung-Chow Peng,
Fu-Lung Hsueh,
Tsung-Hsin Yu,
Jinn-Yeh Chien,
Wen-Hung Huang,
Chi-Chang Lu,
Mu-Shan Lin,
Chin-Ming Fu,
Shu-Chun Yang,
Chung-Wing Wong,
Wan-Te Chen,
Chin-Hua Wen,
Li Yueh Wang,
Chiang Pu:
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
CICC 2010: 1-4 |
| 2 |  | Hsieh-Hung Hsieh,
Fu-Lung Hsueh,
Chewnpu Jou,
Fred Kuo,
Sean Chen,
Tzu-Jin Yeh,
Kevin Kai-Wen Tan,
Po-Yi Wu,
Yu-Ling Lin,
Ming-Hsien Tsai:
A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS.
CICC 2010: 1-4 |
| 2007 |
| 1 |  | Wen-Shen Chou,
Shu-Chieh Yang,
Fu-Lung Hsueh,
Heng-Chang Huang,
Chih-Ji Hsiao:
A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process.
ISCAS 2007: 3594-3597 |