Yu-Chin Hsu

	2011
42		Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell: A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation. DAC 2011: 575-578
	2008
41		Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu: A General Failure Candidate Ranking Framework for Silicon Debug. VTS 2008: 352-358
	2006
40		Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang: Visibility enhancement for silicon debug. DAC 2006: 13-18
39		Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu: Diagnosing Silicon Failures Based on Functional Test Patterns. MTV 2006: 94-98
	2003
38		Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai: Advanced techniques for RTL debugging. DAC 2003: 362-367
	2002
37		Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai: Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. ACM Trans. Design Autom. Electr. Syst. 7(1): 217-230 (2002)
	2000
36		Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai: Timing optimization on routed designs with incremental placementand routing characterization. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 188-196 (2000)
	1999
35		Enoch Hwang, Frank Vahid, Yu-Chin Hsu: FSMD Functional Partitioning for Low Power. DATE 1999: 22-27
34		Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai: Post-routing timing optimization with routing characterization. ISPD 1999: 30-35
	1998
33		Frank Vahid, Thuy Dm Le, Yu-Chin Hsu: Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance. ACM Trans. Design Autom. Electr. Syst. 3(2): 181-208 (1998)
32		Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee: Eliminating false loops caused by sharing in control path. ACM Trans. Design Autom. Electr. Syst. 3(3): 487-495 (1998)
	1997
31		Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita: Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping. Design Autom. for Emb. Sys. 2(3-4): 319-338 (1997)
	1996
30		Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita: Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. DAC 1996: 585-590
29		Frank Vahid, Thuy Dm Le, Yu-Chin Hsu: A Comparison of Functional and Structural Partitioning. ISSS 1996: 121-126
28		Alan Su, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee: Eliminating False Loops Caused by Sharing in Control Path. ISSS 1996: 39-44
	1995
27		Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang: Synthesis of false loop free circuits. ASP-DAC 1995
26		Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang: A new approach to schedule operations across nested-ifs and nested-loops. Microprocessing and Microprogramming 41(1): 37-52 (1995)
25		Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang: A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits. Microprocessing and Microprogramming 41(7): 501-519 (1995)
	1994
24		How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang: Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429
23		Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King: MULTIPAR: behavioral partition for synthesizing multiprocessor architectures. IEEE Trans. VLSI Syst. 2(1): 21-32 (1994)
22		Ting-Hai Chao, Yu-Chin Hsu: Rectilinear Steiner tree construction by local and global refinement. IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 303-309 (1994)
	1993
21		Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee: High throughput pipelined data path synthesis by conserving the regularity of nested loops. ICCAD 1993: 450-453
20		Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu: An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 410-424 (1993)
19		Cheng-Tsung Hwang, Yu-Chin Hsu: Zone scheduling. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 926-934 (1993)
18		Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: PLS: a scheduler for pipeline synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(9): 1279-1286 (1993)
	1992
17		Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho: Zero Skew Clock Net Routing. DAC 1992: 518-523
16		Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang: A new approach to schedule operations across nested-ifs and nested-loops. MICRO 1992: 268-271
15		Fur-Shing Tsai, Yu-Chin Hsu: STAR: An automatic data path allocator. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1053-1064 (1992)
	1991
14		Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu: An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC 1991: 481-486
13		Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: Scheduling for Functional Pipelining and Loop Winding. DAC 1991: 764-769
12		Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu: Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits. ICCAD 1991: 38-41
11		Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao: Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers 40(6): 706-713 (1991)
10		Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu: A formal approach to the scheduling problem in high level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 464-475 (1991)
9		Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu: LiB: a CMOS cell compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 994-1005 (1991)
	1990
8		Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu: LiB: A Cell Layout Generator. DAC 1990: 474-479
7		Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu: Data Path Allocation Based on Bipartite Weighted Matching. DAC 1990: 499-504
6		Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin: Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC 1990: 65-70
5		Fur-Shing Tsai, Yu-Chin Hsu: Data Path Construction and Refinement. ICCAD 1990: 308-311
4		Ting-Hai Chao, Yu-Chin Hsu: Rectilinear Steiner Tree Construction by Local and Global Refinement. ICCAD 1990: 432-435
3		Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai: Hybrid routing. IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 151-157 (1990)
2		Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu: A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 781-786 (1990)
	1989
1		Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai: SILK: a simulated evolution router. IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1108-1114 (1989)

Coauthor Index

1	George Bakewell	[42]
2	Bandana Bhattarai	[42]
3	Ying-Tsai Chang	[40]
4	Chieh Changfan	[34] [36] [37]
5	Ting-Hai Chao	[4] [11] [17] [22]
6	Ben Chen	[30] [31]
7	Xi Chen	[42]
8	Yen-Shen Chen	[7]
9	Yirng-An Chen	[38]
10	Yunn Yen Chen	[23]
11	Ching-Lung Chou	[24]
12	Jay Dutt	[42]
13	Masahiro Fujita	[30] [31]
14	Jan-Ming Ho	[17]
15	Hang-Ching Hsieh	[11]
16	Yung-Chin Hsieh	[2]
17	Yung-Ching Hsieh	[8] [9] [14] [20]
18	Chu-Yi Huang	[7]
19	Shih-Hsu Huang	[16] [25] [26] [27]
20	Cheng-Tsung Hwang	[6] [10] [12] [13] [16] [18] [19] [26]
21	Chi-Yi Hwang	[2] [8] [9] [14] [20]
22	Enoch Hwang	[35]
23	TingTing Hwang	[24]
24	Yuan-Long Jeang	[21]
25	Wells Jong	[40]
26	Chung-Ta King	[23]
27	Thuy Dm Le	[29] [33]
28	Jau-Yien Lee	[21]
29	Jiahn-Humg Lee	[10]
30	Mike Tien-Chien Lee	[28] [30] [31] [32]
31	Hermes Lin	[39] [41]
32	How-Rern Lin	[24]
33	Shi-Zheng Lin	[12]
34	Shi-Zheng Eric Lin	[37]
35	Ten Lin	[39] [41]
36	Youn-Long Lin	[1] [2] [3] [6] [7] [8] [9] [11] [13] [14] [18] [20]
37	Ta-Yung Liu	[27] [28] [32] [39] [41]
38	Gary Miller	[42]
39	Yen-Jen Oyang	[16] [25] [26] [27]
40	Alan Su	[28] [32]
41	Bassam Tabbara	[38]
42	Fur-Shing Tsai	[1] [3] [5] [15] [34] [36] [37] [38] [40]
43	Frank Vahid	[29] [33] [35]
44	Jhing-Fa Wang	[21]
45	Kai Yang	[39] [41]
46	Chia-Chih Yen	[39] [41]

Colors in the list of coauthors

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