Jer-Ming Hsu

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2003

2 Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang: Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC 2003: 812-817

1 Shih-Ching Lo, Jyun-Hwei Tsai, Jer-Ming Hsu, Yiming Li: Quantum Mechanical Gate Current Simulation in MOSFETs with Ultrathin Oxides. VLSI 2003: 244-250

	2003
2		Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang: Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC 2003: 812-817
1		Shih-Ching Lo, Jyun-Hwei Tsai, Jer-Ming Hsu, Yiming Li: Quantum Mechanical Gate Current Simulation in MOSFETs with Ultrathin Oxides. VLSI 2003: 244-250

Coauthor Index

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team —

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1	Yao-Wen Chang	[2]
2	Hsun-Cheng Lee	[2]
3	Yiming Li	[1]
4	Shih-Ching Lo	[1]
5	Jyun-Hwei Tsai	[1]
6	Hannah Honghua Yang (Honghua Yang)	[2]