 | 2011 |
|---|
| 9 |       | Chin-Hsiung Hsu,
Yao-Wen Chang,
Sani R. Nassif:
Simultaneous Layout Migration and Decomposition for Double Patterning Technology.
IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 284-294 (2011) |
| 2010 |
|---|
| 8 | | Chin-Hsiung Hsu,
Yao-Wen Chang,
Sani R. Nassif:
Template-mask design methodology for double patterning technology.
ICCAD 2010: 107-111 |
| 7 | | Chin-Hsiung Hsu,
Huang-Yu Chen,
Yao-Wen Chang:
Multilayer Global Routing With Via and Wire Capacity Considerations.
IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 685-696 (2010) |
| 2009 |
|---|
| 6 | | Huang-Yu Chen,
Chin-Hsiung Hsu,
Yao-Wen Chang:
High-performance global routing with fast overflow reduction.
ASP-DAC 2009: 582-587 |
| 5 | | Chin-Hsiung Hsu,
Yao-Wen Chang,
Sani R. Nassif:
Simultaneous layout migration and decomposition for double patterning technology.
ICCAD 2009: 595-600 |
| 4 | | Jia-Wei Fang,
Chin-Hsiung Hsu,
Yao-Wen Chang:
An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 98-110 (2009) |
| 2008 |
|---|
| 3 | | Chin-Hsiung Hsu,
Huang-Yu Chen,
Yao-Wen Chang:
Multi-layer global routing considering via and wire capacities.
ICCAD 2008: 350-355 |
| 2007 |
|---|
| 2 | | Jia-Wei Fang,
Chin-Hsiung Hsu,
Yao-Wen Chang:
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design.
DAC 2007: 606-611 |
| 1 | | Chin-Hsiung Hsu,
Szu-Jui Chou,
Jie-Hong Roland Jiang,
Yao-Wen Chang:
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits.
PATMOS 2007: 148-159 |
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