 | 2011 |
|---|
| 7 |       | Hao-I Yang,
Shih-Chi Yang,
Mao-Chih Hsia,
Yung-Wei Lin,
Yi-Wei Lin,
Chien-Hen Chen,
Chi-Shin Chang,
Geng-Cing Lin,
Yin-Nien Chen,
Ching-Te Chuang,
Wei Hwang,
Shyh-Jye Jou,
Nan-Chun Lien,
Hung-Yu Li,
Kuen-Di Lee,
Wei-Chiang Shih,
Ya-Ping Wu,
Wen-Ta Lee,
Chih-Chiang Hsu:
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.
SoCC 2011: 197-200 |
| 6 | | Chih-Chiang Hsu,
Kuo-Chan Huang,
Feng-Jian Wang:
Online scheduling of workflow applications in grid environments.
Future Generation Comp. Syst. 27(6): 860-870 (2011) |
| 2010 |
|---|
| 5 | | Chih-Chiang Hsu,
Kuo-Chan Huang,
Feng-Jian Wang:
Online Scheduling of Workflow Applications in Grid Environment.
GPC 2010: 300-310 |
| 4 | | Tsu-Wei Tseng,
Jin-Fu Li,
Chih-Chiang Hsu:
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs.
IEEE Trans. VLSI Syst. 18(6): 921-932 (2010) |
| 2008 |
|---|
| 3 | | Chung-Fu Lin,
Chia-Fu Huang,
De-Chung Lu,
Chih-Chiang Hsu,
Wen-Tsung Chiu,
Yu-Wei Chen,
Yeong-Jar Chang:
A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances.
ITC 2008: 1 |
| 2006 |
|---|
| 2 | | Tsu-Wei Tseng,
Jin-Fu Li,
Chih-Chiang Hsu,
Alex Pao,
Kevin Chiu,
Eliot Chen:
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs.
ITC 2006: 1-9 |
| 2004 |
|---|
| 1 | | Jin-Fu Li,
Chih-Chiang Hsu:
Efficient Test Methodologies for Conditional Sum Adders.
Asian Test Symposium 2004: 319-324 |
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