Wen-Tsan Hsieh

	2011
8		Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh: System-level design exploration for 3-D stacked memory architectures. CODES+ISSS 2011: 389-390
7		Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh: PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. DAC 2011: 47-52
6		Wen-Tsan Hsieh, Jen-Chieh Yeh, Shih-Che Lin, Hsing-Chuang Liu, Yi-Siou Chen: System power analysis with DVFS on ESL virtual platform. SoCC 2011: 93-98
	2010
5		Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang: PAC duo system power estimation at ESL. ASP-DAC 2010: 815-820
	2007
4		Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu: An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model. IEICE Transactions 90-A(5): 1038-1044 (2007)
3		Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou: A Tableless Approach for High-Level Power Modeling Using Neural Networks. J. Inf. Sci. Eng. 23(1): 71-90 (2007)
	2006
2		Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu: A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. PATMOS 2006: 543-552
	2005
1		Wen-Tsan Hsieh, Chih-Chieh Shiue, Chien-Nan Jimmy Liu: A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. ISCAS (4) 2005: 3591-3594

Coauthor Index

1	Yi-Siou Chen	[6]
2	Yi-Fang Chiu	[2] [4]
3	Shan-Chien Fang	[7]
4	Hsien-Ching Hsieh	[8]
5	Chen-Wei Hsu	[7]
6	Chih-Yang Hsu	[3]
7	Shi-Yu Huang	[5] [7]
8	Jing-Yang Jou	[3]
9	Jia-Lu Liao	[7]
10	Chi-Hung Lin	[8]
11	Shih-Che Lin	[6]
12	Chien-Nan Jimmy Liu	[1] [2] [3] [4]
13	Chun-Nan Liu	[8]
14	Hsing-Chuang Liu	[6]
15	Chih-Chieh Shiue	[1]
16	Chia-Chien Weng (Chia-Chieh Weng)	[7]
17	Jen-Chieh Yeh	[5] [6] [7] [8]
18	Chi-Chia Yu	[2] [4]

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