Tsai-Ming Hsieh

	2011
16		Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh: A new ECO technology for functional changes and removing timing violations. ISQED 2011: 634-638
15		Hsin-Hsiung Huang, Jui-Hung Hung, Cheng-Chiang Lin, Tsai-Ming Hsieh: Wire Planning for Electromigration and Interference Avoidance in Analog Circuits. IEICE Transactions 94-A(11): 2402-2411 (2011)
	2010
14		Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh: Technology remapping for engineering change with wirelength consideration. ISCAS 2010: 2602-2605
13		Hsi-An Chien, Cheng-Chiang Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh: Optimal Supply Voltage Assignment under Timing, Power and Area Constraints. IEICE Transactions 93-A(4): 761-768 (2010)
	2008
12		Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh: Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. ISCAS 2008: 1200-1203
11		Hsin-Hsiung Huang, Shu-Ping Chang, Yu-Cheng Lin, Tsai-Ming Hsieh: Timing-driven X-architecture router among rectangular obstacles. ISCAS 2008: 1804-1807
	2006
10		Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh: A congestion-driven buffer planner with space reservation. ISCAS 2006
	2005
9		Chin-Hui Wang, Yung-Ching Chen, Tsai-Ming Hsieh, Chih-Hung Lee, Hsin-Hsiung Huang: A new congestion and crosstalk aware router. ISCAS (6) 2005: 6234-6237
8		Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh: Floorplanning with clock tree estimation. ISCAS (6) 2005: 6244-6247
	2004
7		Yi-Lin Hsieh, Tsai-Ming Hsieh: A New Effective Congestion Model in Floorplan Design. DATE 2004: 1204-1209
	2002
6		Chih-Hung Lee, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh: An efficient hierarchical approach for general floorplan area minimization. APCCAS (2) 2002: 347-352
5		Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh: A New Formulation for SOC Floorplan Area Minimization Problem. DATE 2002: 1100
4		Chih-Hung Lee, Yi-Lin Hsieh, Hui-Chun Lee, Tsai-Ming Hsieh: Sequence-pair based placement with boundary constraints. ISCAS (1) 2002: 341-344
3		Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh: Structural Decomposition with Functional Considerations for Low Power. ISQED 2002: 464-469
	2001
2		Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh: Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. ISCAS (5) 2001: 519-522
	2000
1		Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh: Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). FPGA 2000: 217

Coauthor Index

1	Chung-Chiao Chang	[5] [6]
2	Shu-Ping Chang	[11]
3	Yung-Ching Chen	[9] [10]
4	Hsi-An Chien	[13]
5	Po-Xun Chiu	[2]
6	Wen-Yu Fu	[5] [6]
7	Yi-Lin Hsieh	[4] [7]
8	Yi-Ling Hsieh	[2]
9	Hsin-Hsiung Huang	[3] [9] [10] [11] [12] [13] [15]
10	Hui-Yu Huang	[12]
11	Shih-Hsu Huang	[8]
12	Jui-Hung Hung	[14] [15] [16]
13	Chih-Hung Lee	[3] [4] [5] [6] [8] [9]
14	Hui-Chun Lee	[4]
15	Cheng-Chiang Lin	[13] [15]
16	Chih-Yuan Lin	[8]
17	Yu-Cheng Lin	[11] [12]
18	Yu-Chung Lin	[1] [2] [3] [5]
19	Chin-Hung Su	[8]
20	Su-Feng Tseng	[1]
21	Yung-Sheng Tseng	[14] [16]
22	Chin-Hui Wang	[9]
23	Yao-Kai Yeh	[14] [16]

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