Chang-Yo Hsieh

	2011
4		Wei-Bin Yang, Chang-Yo Hsieh: A synthesizable pseudo fractional-N clock generator with improved duty cycle output. Microelectronics Journal 42(10): 1099-1106 (2011)
	2006
3		Jen-Shiun Chiang, Chang-Yo Hsieh, Jin-Chan Liu, Cheng-Chih Chien: Concurrent bit-plane coding architecture for EBCOT in JPEG2000. ISCAS 2006
2		Jen-Shiun Chiang, Chun-Hau Chang, Chang-Yo Hsieh, Chih-Hsien Hsia: High Efficiency EBCOT with Parallel Coding Architecture for JPEG2000. EURASIP J. Adv. Sig. Proc. 2006: (2006)
	2002
1		Jen-Shiun Chiang, Yu-Sen Lin, Chang-Yo Hsieh: Efficient pass-parallel architecture for EBCOT in JPEG2000. ISCAS (1) 2002: 773-776

Coauthor Index

1	Chun-Hau Chang	[2]
2	Jen-Shiun Chiang	[1] [2] [3]
3	Cheng-Chih Chien	[3]
4	Chih-Hsien Hsia	[2]
5	Yu-Sen Lin	[1]
6	Jin-Chan Liu	[3]
7	Wei-Bin Yang	[4]

Colors in the list of coauthors

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