 | 2012 |
|---|
| 7 |       | Ang-Chih Hsieh,
TingTing Hwang:
TSV Redundancy: Architecture and Design Issues in 3-D IC.
IEEE Trans. VLSI Syst. 20(4): 711-722 (2012) |
| 2011 |
|---|
| 6 | | Ang-Chih Hsieh,
Chun-Cheng Liu,
TingTing Hwang:
Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation.
ASP-DAC 2011: 231-236 |
| 5 | | Ang-Chih Hsieh,
Yi-Ta Wu,
Shau-Yin Tseng,
TingTing Hwang:
Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms.
ICPP 2011: 552-561 |
| 2010 |
|---|
| 4 | | Ang-Chih Hsieh,
TingTing Hwang,
Ming-Tung Chang,
Min-Hsiu Tsai,
Chih-Mou Tseng,
Hung-Chun Li:
TSV redundancy: Architecture and design issues in 3D IC.
DATE 2010: 166-171 |
| 2009 |
|---|
| 3 | | Ang-Chih Hsieh,
TingTing Hwang:
Thermal-aware memory mapping in 3D designs.
DATE 2009: 1361-1366 |
| 2007 |
|---|
| 2 | | Ang-Chih Hsieh,
Tzu-Teng Lin,
Tsuang-Wei Chang,
TingTing Hwang:
A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
| 2006 |
|---|
| 1 | | Chi Ta Wu,
Ang-Chih Hsieh,
TingTing Hwang:
Instruction buffering for nested loops in low-power design.
IEEE Trans. VLSI Syst. 14(7): 780-784 (2006) |
Data released under the ODC-BY 1.0 license — See also our legal information page