 | 1997 |
|---|
| 4 |       | Chun-Te Chen,
Liang-Gee Chen,
Jue-Hsuan Hsiao:
A bit-level pipelined VLSI architecture for the running order algorithm.
IEEE Transactions on Signal Processing 45(8): 2140-2144 (1997) |
| 1995 |
|---|
| 3 | | Chun-Te Chen,
Liang-Gee Chen,
Jue-Hsuan Hsiao:
A hardware-oriented design for weighted median filters.
ASP-DAC 1995 |
| 1994 |
|---|
| 2 |  | Jue-Hsuan Hsiao,
Liang-Gee Chen,
Tzi-Dar Chiueh,
Chun-Te Chen:
High Throughput CORDIC-Based Systolic Array Design for the Discrete Cosine Transform.
ISCAS 1994: 85-88 |
| 1993 |
|---|
| 1 | | Jue-Hsuan Hsiao,
Liang-Gee Chen,
Tzi-Dar Chiueh,
Chun-Te Chen:
Novel Systolic Array Design for the Discrete Hartley Transform with High Throughput Rate.
ISCAS 1993: 1567-1570 |
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