Jason Howard

	2012
7		Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar: A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC 2012: 66-68
	2011
6		Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart: A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. J. Solid-State Circuits 46(1): 173-183 (2011)
5		Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar: Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. J. Solid-State Circuits 46(1): 184-193 (2011)
	2010
4		Jason Howard, Saurabh Dighe, Yatin Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson: A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC 2010: 108-109
3		Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar: Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC 2010: 174-175
2		Timothy G. Mattson, Michael Riepen, Thomas Lehnig, Paul Brett, Werner Haas, Patrick Kennedy, Jason Howard, Sriram R. Vangal, Nitin Borkar, Gregory Ruhl, Saurabh Dighe: The 48-core SCC Processor: the Programmer's View. SC 2010: 1-11
	2006
1		Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard: Testing High-Speed IO Links Using On-Die Circuitry. VLSI Design 2006: 807-810

Coauthor Index

1	V. Ambili	[7]
2	Thomas Apel	[4]
3	Paolo A. Aseron	[3] [5] [7]
4	Nitin Borkar	[2] [3] [4] [5] [6] [7]
5	Shekhar Y. Borkar (Shekhar Borkar)	[3] [4] [5] [6] [7]
6	Keith A. Bowman	[3] [5]
7	Paul Brett	[2]
8	Bryan Casper	[1]
9	Vivek De (Vivek K. De)	[3] [4] [5] [6] [7]
10	Saurabh Dighe	[2] [3] [4] [5] [6] [7]
11	Guido Droege	[4] [6]
12	Vasantha Erraguntla	[3] [4] [5] [6] [7]
13	David Finan	[4]
14	Matthias Gries	[4] [6]
15	Werner Haas	[2]
16	Kersten Henriss	[4]
17	Yatin Hoskote	[4]
18	Priya Iyer	[1]
19	Tiju Jacob	[3] [4] [5]
20	Shailendra Jain	[1] [4] [6] [7]
21	David Jenkins	[4]
22	Patrick Kennedy	[2]
23	Surhud Khare	[7]
24	Michael Konow	[4] [6]
25	Arun Kumar	[7]
26	Shasi Kumar	[3] [5] [7]
27	Thomas Lehnig	[2]
28	Joerg Lindemann	[4]
29	Tor Lund-Larsen	[4] [6]
30	Sraven Marella	[4]
31	Timothy G. Mattson	[2] [4]
32	Sriram Muthukumar	[7]
33	Fabric Pailet	[4]
34	Rajaraman Ramanarayanan	[7]
35	Shiva Ramani	[7]
36	Michael Riepen	[2] [4] [6]
37	Gregory Ruhl	[2] [4] [6] [7]
38	Praveen Salihundam	[4] [7]
39	Gerhard Schrom	[4]
40	M. Srinivasan	[7]
41	Sebastian Steibl	[4] [6]
42	James Tschanz (James W. Tschanz)	[3] [5]
43	Sriram R. Vangal	[2] [3] [4] [5] [6] [7]
44	Rob F. Van der Wijngaart	[4] [6]
45	Howard Wilson	[4] [7]
46	Satish Yada	[4] [7]

Last update Thu May 31 18:55:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page