Mohammad Hosseinabady

	2012
25		Mohammad Hosseinabady, Jose Luis Nunez-Yanez: Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles. IET Computers & Digital Techniques 6(1): 1-11 (2012)
	2011
24		Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Trans. VLSI Syst. 19(8): 1469-1480 (2011)
	2010
23		Mohammad Hosseinabady, José L. Núñez-Yáñez: SystemC Architectural Transaction Level Modelling for Large NoCs. FDL 2010: 142-147
22		Mohammad Hosseinabady, José L. Núñez-Yáñez: Effective modelling of large NoCs using SystemC. ISCAS 2010: 161-164
21		Mohammad Hosseinabady, Jose Luis Nunez-Yanez, Antonio Marcello Coppola: Task Dispersal Measurement in Dynamic Reconfigurable NoCs. ISVLSI 2010: 167-172
	2009
20		Mohammad Hosseinabady, José L. Núñez-Yáñez: Run-time resource management in fault-tolerant network on reconfigurable chips. FPL 2009: 574-577
	2008
19		Mohammad Hosseinabady, José L. Núñez-Yáñez: Fault-tolerant dynamically reconfigurable NoC-based SoC. ASAP 2008: 31-36
18		Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan: De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE 2008: 1370-1373
17		Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan: Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS 2008: 1684-1687
16		Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi: A Selective Trigger Scan Architecture for VLSI Testing. IEEE Trans. Computers 57(3): 316-328 (2008)
	2007
15		Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi: Using the inter- and intra-switch regularity in NoC switch testing. DATE 2007: 361-366
14		Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan: Single Event Upset Detection and Correction. ICIT 2007: 13-18
13		Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale: Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. IOLTS 2007: 205-206
12		Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi: An Analytical Model for Reliability Evaluation of NoC Architectures. IOLTS 2007: 49-56
11		Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi: A UML Based System Level Failure Rate Assessment Technique for SoC Designs. VTS 2007: 243-248
10		Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi: Low test application time resource binding for behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007)
9		Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Simultaneous Reduction of Dynamic and Static Power in Scan Structures CoRR abs/0710.4653: (2007)
8		Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi: Low overhead DFT using CDFG by modifying controller. IET Computers & Digital Techniques 1(4): 322-333 (2007)
	2006
7		Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi: A concurrent testing method for NoC switches. DATE 2006: 1171-1176
6		Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto: Single-Event Upset Analysis and Protection in High Speed Circuits. European Test Symposium 2006: 29-34
5		Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Scan-Based Structure with Reduced Static and Dynamic Power Consumption. J. Low Power Electronics 2(3): 477-487 (2006)
	2005
4		Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi: TED+: a data structure for microprocessor verification. ASP-DAC 2005: 567-572
3		Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi: Simultaneous Reduction of Dynamic and Static Power in Scan Structures. DATE 2005: 846-851
	2003
2		Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi: Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. DFT 2003: 352-360
1		Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi: Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. VLSI-SOC 2003: 215-220

Coauthor Index

1	Ali Afzali-Kusha	[3] [5] [9]
2	Abbas BanaiyanMofrad (Abbas Banaiyan)	[7]
3	Alfredo Benso	[6] [13]
4	Mahdi Nazm Bojnordi	[7]
5	Stefano Di Carlo	[6] [13]
6	Antonio Marcello Coppola	[21]
7	Atefe Dalirsani	[12] [15]
8	Abusaleh M. Jabir	[17]
9	Javid Jaffari	[3] [5] [9]
10	Mohammad Reza Kakoee	[18] [24]
11	Fabrizio Lombardi	[8] [16]
12	Pejman Lotfi-Kamran	[4] [6] [8] [10] [11]
13	Mehran Massoumi	[4]
14	Jimson Mathew	[14] [17] [18] [24]
15	Giorgio Di Natale	[6] [13]
16	Zainalabedin Navabi	[1] [2] [3] [4] [5] [7] [8] [9] [10] [11] [12] [13] [15] [16]
17	Mohammad Hossein Neishaburi	[11] [13]
18	José L. Núñez-Yáñez (Jose Luis Nunez-Yanez)	[19] [20] [21] [22] [23] [25]
19	Dhiraj K. Pradhan	[14] [17] [18] [24]
20	Paolo Prinetto	[6] [13]
21	Pedram A. Riahi	[2]
22	Shervin Sharifi	[1] [2] [3] [5] [9] [16]
23	Hamid Shojaei	[4]
24	Jawar Singh	[14] [17]

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